• Title/Summary/Keyword: thermal circuit

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Structural Improvement for Crack of Integrated Circuit in Single Board Computer by Structure Analysis (단일보드컴퓨터 구조해석을 통한 집적회로 균열현상의 구조적 개선)

  • Ryu, Jeong-min;Lee, Yong-jun;Sohn, Kwonil
    • Journal of Advanced Navigation Technology
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    • v.23 no.5
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    • pp.460-465
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    • 2019
  • In this study, we aim to derive a solution from the structural analysis for electrical failure of single board computers for computing navigation information. By analyzing the characteristic factor, we identify that crack occur on the central processing unit board due to a certain structural problem, and that the physical effect by the crack make communication function be impossible to perform, which it causes booting error. In order to find the location of excessive stress causing the crack, structural analysis for the single board computer is done. From the structural analysis, the areas where stress concentration occurs are identified, and improvement methods changing the structures are developed. As a result, we shows that stresses are reduced entirely on the stress distribution for the improved structure. In addition, heat analysis shows that changing the structure to reduce stresses is not affect to the heat radiation, and the thermal resistance of the actual equipment is verified by measuring the temperature of the heat sink applied with the improved structure.

A Consideration on the Causes of 22.9kV Cable Terminal Burning Accident (22.9kV 케이블 단말 부위 소손 사고의 원인에 관한 고찰)

  • Shim, Hun
    • Journal of Internet of Things and Convergence
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    • v.8 no.2
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    • pp.7-12
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    • 2022
  • The main cause of cable accidents is the accelerated deterioration of the cable itself or internal and external electrical, mechanical, chemical, thermal, moisture intrusion, etc., which reduces insulation performance and causes insulation breakdown, leading to cable accidents. Insulation deterioration can occur even when there is no change in the appearance of the cable, so there is a difficulty in preventing cable accidents due to insulation deterioration. Since cable accidents can occur in areas with poor insulation due to the effects of overvoltage and overcurrent, it is necessary to comprehensively analyze transformers and circuit breakers, and ground faults caused by phase-to-phase imbalance. Ground fault accidents due to insulation breakdown of cables can occur due to defects in the cable itself and poor cable construction, as well as operational influences, arcs during operation of electrical equipment (switchers, circuit breakers, etc.). analysis is needed. This study intends to examine the causes of cable accidents through analysis of cable accidents that occurred in a manufacturing factory.

Evaluation of Internal Blast Overpressures in Test Rooms of Elcetric Vehicles Battery with Pressure Relief Vents (압력배출구를 설치한 전동화 차량 배터리 시험실의 내부 폭압 평가)

  • Pang, Seungki;Shin, Jinwon;Jeong, Hyunjin
    • Journal of the Korean Society for Geothermal and Hydrothermal Energy
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    • v.18 no.3
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    • pp.7-18
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    • 2022
  • Secondary batteries used in electric vehicles have a potential risk of ignition and explosion. Various safety measures are being taken to prevent these risks. A numerical study was performed using a computational fluid dynamics code on the cases where pressure relief vents that can reduce the blast overpressures of batteries were installed in the through-compression test room, short-circuit drop test room, combustion test room, and immersion test room in facilities rleated to battery used in electric vehicles. This study was conducted using the weight of TNT equivalent to the energy release from the battery, where the the thermal runaway energy was set to 324,000 kJ for the capacity of the lithium-ion battery was 90 kWh and the state of charge (SOC) of the battery of 100%. The explosion energy of TNT (△HTNT) generally has a range of 4,437 to 4,765 kJ/kg, and a value of 4,500 kJ/kg was thus used in this study. The dimensionless explosion efficiency coefficient was defined as 15% assuming the most unfavorable condition, and the TNT equivalent mass was calculated to be 11 kg. The internal explosion generated in a test room shows the very complex propagation behavior of blast waves. The shock wave generated after the explosion creates reflected shock waves on all inner surfaces. If the internally reflected shock waves are not effectively released to the outside, the overpressures inside are increased or maintained due to the continuous reflection and superposition from the inside for a long time. Blast simulations for internal explosion targeting four test rooms with pressure relief vents installed were herein conducted. It was found that that the maximum blast overpressure of 34.69 bar occurred on the rear wall of the immersion test room, and the smallest blast overpressure was calculated to be 3.58 bar on the side wall of the short-circuit drop test room.

A study on the effective fault current limiting characteristics of stacked coated conductors with stainless steel stabilizer (스테인리스 스틸 안정화재를 가진 coated conductor의 적층 유무에 따른 효과적인 사고전류 제한을 위한 연구)

  • Na, J.B.;Ahn, M.C.;Kim, M.J.;Kim, Y.J.;Yang, S.E.;Park, D.K.;Kim, H.M.;Seok, B.Y.;Ko, T.K.
    • Progress in Superconductivity and Cryogenics
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    • v.9 no.1
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    • pp.9-13
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    • 2007
  • Coated conductor(CC) is recently in actively progress for the research and development, and its can be used various stabilizer lot the specific requirements for each application. Among various superconducting applications, coated conductor applied to superconducting fault current limiters(SFCLS) bypasses fault current to its stabilizer, where the surge is abruptly reduced ; thus, stainless steel, which has large resistivity can be a suitable stabilizer for SFCLS. Despite high n-value of the YBCO, CC stabilized with stainless steel did not effectively limit the first peak fault current. In the short circuit test results of AMSC's 344S, a half period delay was observed between the fault and the generation of resistance(60Hz). In this paper, we performed short-circuit experiments with stacked and unstacked CC and compared the test results to analyze effective fault current limiting characteristics. we compared time of the generated resistance as the fault current limiting characteristics and made the samples one is the stacked CC and the other is unstacked CC. These samples were used equal numbers of pieces of CC. In addition, comparison and analysis was made for the stacked structure by measuring fault current limiting characteristics with respect to thermal insulation by impregnating with epoxy resin.

Low-Power CMOS On-Chip Voltage Reference Circuits (저전력 CMOS On-Chip 기준전압 발생회로)

  • Kwon, Duck-Ki;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.4 no.2 s.7
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    • pp.181-191
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    • 2000
  • In this paper, two schemes of generating reference voltages using enhancement-mode MOS transistors and resistors are proposed. The first one is a voltage-mode scheme where the temperature compensation is made by summing a voltage component proportional to a threshold voltage and a voltage component proportional to a thermal voltage. In the second one, that is a current-mode scheme, the temperature compensation is made by summing a current component proportional to a threshold voltage and a current component proportional to a thermal voltage. The designed circuits have been simulated using a $0.65{\mu}m$ n-well CMOS process parameters. The voltage-mode circuit has a temperature coefficient less than $48.0ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.21%/V for a temperature range of $-30^{\circ}C{\sim}130^{\circ}C$ and a VDD range of $3V{\sim}12V$. The current-mode circuit has a temperature coefficient less than $38.2ppm/^{\circ}C$ and a VDD coefficient less than 0.8%/V for $-30^{\circ}C{\sim}130^{\circ}C\;and\; 4V{\sim}12V$. The power consumption of the voltage-mode and current-mode circuits are $27{\mu}W\;and\;65{\mu}W$ respectively for 5V and $30^{\circ}C$. Measurement results show that the voltage-mode reference circuit has a VDD coefficient less than 0.63%/V for $30^{\circ}C{\sim}100^{\circ}C$ and has a temperature coefficient less than $490ppm/^{\circ}C\;for\;3V{\sim}6V$. The proposed reference circuits are simple and thus easy to design. The proposed current-mode reference circuit can be designed to generate a wide range of reference voltages.

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Joining and Performance of Alkali Metal Thermal-to-electric Converter (AMTEC) (알칼리금속 열전기변환장치의 접합과 출력성능)

  • Suh, Min-Soo;Lee, Wook-Hyun;Woo, Sang-Kuk
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.41 no.7
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    • pp.665-671
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    • 2017
  • The alkali-Metal Thermal-to-electric Converter (AMTEC) is one of the promising static energy conversion technologies for the direct conversion of thermal energy to electrical energy. The advantages over a conventional energy converter are its high theoretical conversion efficiency of 40% and power density of 500 W/kg. The working principle of an AMTEC battery is the electrochemical reaction of the sodium through an ion conducting electrolyte. Sodium ion pass through the hot side of the beta"-alumina solid electrolyte (BASE) primarily as a result of the pressure difference. This pressure difference across the BASE has a significant effect on the overall performance of the AMTEC system. In order to build the high pressure difference across the BASE, hermeticity is required for each joined components for high temperature range of $900^{\circ}C$. The AMTEC battery was manufactured by utilizing robust joining technology of BASE/insulator/metal flange interfaces of the system for both structural and electrical stability. The electrical potential difference between the anode and cathode sides, where the electrons emitted from sodium ionization and recombined into sodium, was characterized as the open-circuit voltage. The efforts of technological improvement were concentrated on a high-power output and conversion efficiency. This paper discusses about the joining and performance of the AMTEC systems.

Design and Implement of 50MHz 10 bits DAC based on double step Thermometer Code (50MHz 2단 온도계 디코더 방식을 사용한 10 bit DAC 설계)

  • Jung, Jun-Hee;Kim, Young-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.6
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    • pp.18-24
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    • 2012
  • This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

Generation of Testability on High Density /Speed ATM MCM and Its Library Build-up using BCB Thin Film Substrate (고속/고집적 ATM Switching MCM 구현을 위한 설계 Library 구축 밀 시험성 확보)

  • 김승곤;지성근;우준환;임성완
    • Journal of the Microelectronics and Packaging Society
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    • v.6 no.2
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    • pp.37-43
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    • 1999
  • Modules of the system that requires large capacity and high-speed information processing are implemented in the form of MCM that allows high-speed data processing, high density circuit integration and widely applied to such fields as ATM, GPS and PCS. Hence we developed the ATM switching module that is consisted of three chips and 2.48 Gbps data throughput, in the form of 10 multi-layer by Cu/Photo-BCB and 491pin PBGA which size is $48 \times 48 \textrm {mm}^2$. hnologies required for the development of the MCM includes extracting parameters for designing the substrate/package through the interconnect characterization to implement the high-speed characteristics, thermal management at the high-density MCM, and the generation of the testability that is one of the most difficult issues for developing the MCM. For the development of the ATM Switching MCM, we extracted signaling delay, via characteristics and crosstalk parameters through the interconnect characterization on the MCM-D. For the thermal management of 15.6 Watt under the high-density structure, we carried out the thermal analysis. formed 1.108 thermal vias through the substrate, and performed heat-proofing processing for the entire package so that it can keep the temperature less than $85^{\circ}C$. Lastly, in order to ensure the testability, we verified the substrate through fine pitch probing and applied the Boundary Scan Test (BST) for verifying the complex packaging/assembling processes, through which we developed an efficient and cost-effective product.

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A Study on the Compensation of Thermal Errors for Phase Measuring Profilometry (PMP 형상 측정법의 열 변위 보정에 관한 연구)

  • Kim, Gi-Seung;Park, Yoon-Chang
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.20 no.6
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    • pp.598-603
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    • 2019
  • Three-dimensional shape measurement technology is used in various industries. Among them, optical three-dimensional shape measurement techniques based on the optical trigonometry are mainly used in the field of semiconductor product inspection, where large quantities of three-dimensional shape measurements are made daily in factories and fine measurements are also required. The light source and the drive circuit, which are components of three-dimensional measurement equipment based on this optical trigonometry, produce heat generated by prolonged operation, and may be exposed to conditions where the ambient temperature is not constant, resulting in temperature-induced measurement errors. In this study, the compensation method of the Thermal Errors for Phase Measuring Profilometry is proposed. Three-Dimensional Shape Measurement Equipment based on Phase Measuring Profilometry is implemented to measure the height of an object and ambient temperature for 10 Hours, and a regression line was obtained line by making simple linear regression using measured temperature and height values. This regression line was used to correct the error of the height measurement according to the temperature, and thermal error was from 139.88 um(Micrometer) to 13.12 um.

Life Prediction of Failure Mechanisms of the CubeSat Mission Board using Sherlock of Reliability and Life Prediction Tools (신뢰성 수명예측 도구 Sherlock을 이용한 큐브위성용 임무보드의 고장 메커니즘별 수명예측)

  • Jeon, Su-Hyeon;Kwon, Yae-Ha;Kwon, Hyeong-Ahn;Lee, Yong-Geun;Lim, In-OK;Oh, Hyun-Ung
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.44 no.2
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    • pp.172-180
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    • 2016
  • A cubesat classified as a pico-satellite typically uses commercial-grade components that satisfy the vibration and thermal environmental specifications and goes into mission orbit even after undergoing minimum environment tests due to their lower cost and short development period. However, its reliability exposed to the physical environment such as on-orbit thermal vacuum for long periods cannot be assured under minimum tests criterion. In this paper, we have analysed the reliability and life prediction of the failure mechanisms of the cubesat mission board during its service life under the launch and on-orbit environment by using the sherlock software which has been widely used in automobile fields to predict the reliability of electronic devices.