• Title/Summary/Keyword: thermal chemical vapor deposition

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Variations in electrical properties and interface reactions of $Ta_{2}O_{5}-Si$ by RTA post annealing (RTA 후속 열처리에 의한 $Ta_{2}O_{5}-Si$ 계면 반응과 전기적 특성 변화)

  • Jeon, Seok-Ryong;Lee, Jeong-Yeop;Han, Seong-Uk;Park, Jong-Wan
    • Korean Journal of Materials Research
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    • v.5 no.3
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    • pp.357-363
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    • 1995
  • PECVD(Plasma-enhanced Chemical Vapor Deposition)법을 이용하여 증착한 $Ta_{2}$O_{5}$ 박막의 전기적 특성과 미세구조에 미치는 RTA(Rapid Thermal annealing) 후속 고온 열처리의 영향을 조사하였다. $Ta_{2}$O_{5}$ 박막의 미세구조와 interface 거동을 관찰하기 위하여XRD(X-ray Diffractometer), TEM(Transmission Electron Microscope), AES(Auger Electron Spectroscope) 분석을 실시하였으며, 전기적 특성을 관찰하기 위하여 I-V, C-V 측정을 하였다. $600^{\circ}C$에서 60초간 열처리를 실시하였을 경우 가장 우수한 유전 특성 및 누설 전류 특성을 보였으며, 유전 상수는 26이었고 누설 전류는 5 $\times$ $10^{-11}$A/$cm^{2}$이었다. $600^{\circ}C$ 이상의 온도에서 행한 열처리에 의하여 박막의 누설 전류와 유전 특성은 복합적으로 영향을 받았음을 알 수 있었다. 이는 $600^{\circ}C$의 열처리에서 이루어지고있는 박막의 결함감소와 고밀화 현상과 함께 80$0^{\circ}C$ 이상의 열처리에서 발생하는 조밀육방정 결정 구조를 가지는 $\delta$-$Ta_{2}$O_{5}$의 결정화에 기인함을 알 수 있었다. 또한 TEM과 AES분석 결과로부터 이들 박막의 누설 전류와 유전상수의 변화는 열처리에 의하여 일어나는 Ta-O-Si transition층의 생성과 성장에 기인함을 알 수 있었다. 따라서 $Ta_{2}$O_{5}$ 박막의 전기적 특성의 변화는 RTA 후속 열처리에 따른 계면 반응과 결정화 그리고 박막의 조밀화에 그 영향이 있음을 알 수 있었다.

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Characteristics of the Silicon Epitaxial Films Grown by RTCVD Method (RTCVD 법으로 성장한 실리콘 에피막의 특성)

  • Chung, W.J.;Kwon, Y.K.;Bae, Y.H.;Kim, K.I.;Kang, B.K.;Sohn, B.K.
    • Journal of Sensor Science and Technology
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    • v.5 no.1
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    • pp.63-70
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    • 1996
  • Silicon epitaxial films of submicron level were successfully grown by the RTCVD method. For the growth of silicon epitaxial layers, $SiH_{2}Cl_{2}\;/\;H_{2}$ gas mixtures and various process parameters including $H_{2}$ prebake process were used. The growth conditions were varied to investigate their effects on the interface abruptness of doping profile, the film growth rates and crystalline properties. The crystallinity of the undoped silicon was excellent at the growth temperature of $900^{\circ}C$. The doping profiles were measured by SIMS technique. The abruptness of doping profile would be controlled within about $200{\AA}/decade$ in the structure of undoped Si / $n^{+}-Si$ substrate.

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Transfer-Free, Large-Scale, High-Quality Monolayer Graphene Grown Directly onto the Ti (10 nm)-buffered Substrates at Low Temperatures (Ti (10 nm)-buffered 기판들 위에 저온에서 직접 성장된 무 전사, 대 면적, 고 품질 단층 그래핀 특성)

  • Han, Yire;Park, Byeong-Ju;Eom, Ji-Ho;Yoon, Soon-Gil
    • Korean Journal of Materials Research
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    • v.30 no.3
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    • pp.142-148
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    • 2020
  • Graphene has attracted the interest of many researchers due to various its advantages such as high mobility, high transparency, and strong mechanical strength. However, large-area graphene is grown at high temperatures of about 1,000 ℃ and must be transferred to various substrates for various applications. As a result, transferred graphene shows many defects such as wrinkles/ripples and cracks that happen during the transfer process. In this study, we address transfer-free, large-scale, and high-quality monolayer graphene. Monolayer graphene was grown at low temperatures on Ti (10nm)-buffered Si (001) and PET substrates via plasma-assisted thermal chemical vapor deposition (PATCVD). The graphene area is small at low mTorr range of operating pressure, while 4 × 4 ㎠ scale graphene is grown at high working pressures from 1.5 to 1.8 Torr. Four-inch wafer scale graphene growth is achieved at growth conditions of 1.8 Torr working pressure and 150 ℃ growth temperature. The monolayer graphene that is grown directly on the Ti-buffer layer reveals a transparency of 97.4 % at a wavelength of 550 nm, a carrier mobility of about 7,000 ㎠/V×s, and a sheet resistance of 98 W/□. Transfer-free, large-scale, high-quality monolayer graphene can be applied to flexible and stretchable electronic devices.

$CO_2$ 클러스터 표면 처리를 이용한 그래핀 특성 향상에 관한 연구

  • Choe, Hu-Mi;Kim, Jang-A;Jo, Yu-Jin;Hwang, Tae-Hyeon;Lee, Jong-U;Kim, Tae-Seong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.655-655
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    • 2013
  • 그래핀은 높은 전자 이동도, 열전도도, 기계적 강도, 유연성 등의 고유한 특성으로 다양한 분야에 응용하기 위한 연구가 수행되고 있으며, 특히 전자 소자에의 적용에 관한 연구가 활발히 이루어지고 있다. 전자 소자에 적용하기 위해서는 성장 및 물성에 관한 규명, 응용 소자에 따른 특성 평가가 필요하다. 이러한 소자 특성은 그래핀 물성에 의한 영향이 기본적이지만 에칭, 전사 등의 공정 중 발생하는 오염, 표면 특성, 잔여물 등에 의한 물성 변화 또한 분석 및 제어에 관한 연구가 필요하다. 열화학증착법(thermal chemical vapor deposition)을 이용한 그래핀 합성은 구리 기판을 사용하며, 합성된 그래핀의 에칭, 박리 및 전사 공정이 있다. 이러한 공정 중 발생하는 오염 입자가 그래핀 표면에 흡착되거나, 제거되지 않은 PMMA 잔여물이 그래핀의 특성에 영향을 미치게 된다. 따라서 본 연구에서는 $CO_2$ 클러스터의 표면 충돌을 이용하여 이러한 오염 물질 및 잔여물을 제거하고 그래핀 표면을 평탄화하는 것에 관한 연구를 수행하였다. 가스 클러스터란 작동기체의 분자가 수십에서 수백 개 뭉쳐 있는 형태를 뜻하며 이렇게 형성된 클러스터는 수 nm 크기를 형성하게 된다. 그리고 짧은 시간의 응축에 의해 수십 nm 크기 까지 성장 하게 된다. 클러스터를 이용한 표면 처리는 충돌에 의한 제거에 기반 한다. 따라서 생성 및 가속되는 클러스터로부터 대상으로 전달되는 운동량의 정도가 세정 특성에 영향을 미치며 이는 생성되는 클러스터의 크기에 종속적이다. 생성 클러스터의 크기 분포는 분사거리, 유량, 분사 각도, 노즐 냉각 온도 등의 변수에 관한 함수이다. 본 연구에서는 이러한 변수들을 제어하여 클러스터를 이용한 그래핀 표면 처리 실험을 수행하였다. 평가는 클러스터 표면 처리 전과 후의 특성 비교에 기반 하였으며, 광학 현미경을 이용한 표면 형상 측정, 라만분광 분석, AFM을 이용한 표면 조도 측정, 그래핀 면저항 측정 결과를 비교하였다. 평가 결과를 통하여 표면 처리를 하지 않은 그래핀에 비하여 면저항과 표면 조도가 낮아지는 것을 확인 할 수 있었다. 또한 클러스터 세정은 300 mm 웨이퍼 크기 이상의 대면적을 짧은 시간에 건식으로 세정할 수 있다는 장점이 있어 향후 최적화를 통해 그래핀 양산 시 특성 향상을 위한 후처리 방법으로 사용될 수 있음을 확인하였다.

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Characteristics of Polarization and Birefringence for Submicron a-Ge Thin Film on Quartz Substrate Formed by Focused-Ion-Beam (석영 기판 위에 집속 이온빔 기술에 의해 형성된 비정질 게르마늄 박막 미세 패턴의 편광 및 복굴절 특성)

  • Shin, Kyung;Ki, Jin-Woo;Park, Chung-Il;Lee, Hyun-Yong;Chung, Hong-Bay
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.617-620
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    • 1999
  • In this study, the polarization e(fecal and the birefringence effect of amorphous germanium (a-Ge) thin films were investigated by using linearly polarized He-Ne laser beam. The a-7e thin films were deposited on the quarts substrate by plasma enhanced chemical vapor deposition (PECVD) and thermal vacuum evaporation In order to obtain the optimum grating arrays, inorganci resists such as Si$_3$N$_4$ and a-Se$_{75}$ Ge$_{25}$ , were prepared with the optimized thickness by Monte Carlo (MC) simulation. As the results of MC simulation, the thickness ofa-Se$_{75}$ Ge$_{25}$ resist was determined with Z$_{min}$ of 360$\AA$ . The resists were exposed to Ga$^{+}$-FIB with accelerating energies of 50 keV, developed by wet etching, and a-Ge thin film was etched by reactive ion-etching (RIE). Finally, we were obtained grating arrays which grating width and linewidth are 0.8${\mu}{\textrm}{m}$, respectively and we studied the polarization and birefringence effect in transmission grating array made of high refractive amorphous material, and the applicability as waveplates and polarizers in optical device.e.e.

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Synthesis of Silica/Alumina Composite Membrane Using Sol-Gel and CVD Method for Hydrogen Purification at High Temperature (Sol-gel 및 CVD법을 이용한 고온 수소 분리용 silica/alumina 복합막의 합성)

  • 서봉국;이동욱;이규호
    • Membrane Journal
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    • v.11 no.3
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    • pp.124-132
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    • 2001
  • Silica membranes were prepared on a porous ${\alpha}$-alumina tube with pore size of 150nm by sol-gel and chemical vapor deposition(CVD) method for hydrogen separation at high temperatures. Silica and ${\gamma}$-lumina membranes formed by the sol-gel method possessed a large amount of mesopores of a Knudsen diffusion regime. In order to improve the $H_2$ selectivity, silica was deposited in the sol-gel derived silica/${\gamma}$-alumina layer by thermal decomposition of tetraethyl orthosilicate(TEOS) at $600^{\circ}C$. The CVD with forced cross flow through the porous wall of the support was very effective in plugging mesopores that were left unplugged in the membranes. The CVD modified silica/alumina composite membrane completely rejected nitrogen permeation and thus showed a high $H_2$ selectivity by molecular sieve effect. the permeation of hydrogen was explained by activated diffusion and the activation energy was 9.52kJ/mol.

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The effect of misorientation-angle dependence of p-GaN layers grown on r-plane sapphire substrates

  • Son, Ji-Su;Kim, Jae-Beom;Seo, Yong-Gon;Baek, Gwang-Hyeon;Kim, Tae-Geun;Hwang, Seong-Min
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.171-171
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    • 2010
  • GaN 기반 Light emitting diodes(LEDs)의 p-type doping layer는 일반적으로 hole을 발생시키는 acceptor로 Mg이 사용하되고 있다. 보통 Mg이 도핑된 p-type GaN은 >$1\;{\Omega}{\cdot}cm$의 저항이 존재하는데 그 이유는 Mg의 열적 이온화를 위한 activation 에너지가 높아서 상온에서 valence band의 hole concentration는 전체 억셉터 농도의 1%가 되지 않기 ��문이다. 본 논문에서는 높은 hole 농도를 얻기 위해서 metalorganic chemical-vapor deposition (MOCVD)를 장비를 사용하여 사파이어 기판의 misorientation-angle에 따른 p-type a-plane(11-20) GaN 특성을 분석하였다. misorientation-angle은 c축 방향으로 $+0.15^{\circ}$, $-0.15^{\circ}$, $-0.2^{\circ}$, $-0.4^{\circ}$ off된 r-plane(1-102) 사파이어 기판 을 사용하였다. p-type 도핑물질로 bis-magnesium (Cp2Mg) 소스를 사용하였고 성장 과정중 발생하는 hydrogen passivation으로 인한 Mg-H complexes현상을 해결하기위해 conventional furnace annealing (CFA)와 rapid thermal annealing (RTA)를 이용하여 열처리 공정을 진행하였다. 열처리 공정은 Air와 N2 분위기에서 $650^{\circ}C$에서 $900^{\circ}C$ 사이의 다양한 온도에서 수행하였고 Hall 측정을 위해 Ni을 전극 물질로 사용하였다. 상온에서 Accent HL5500IU Hall system을 사용하여 hole concentration, mobility, specific resistance을 측정하였다. 열처리 공정 후 Hall측정 결과 $+0.15^{\circ}$, $-0.15^{\circ}$, $-0.2^{\circ}$, $-0.4^{\circ}$ off된 각 샘플들은 온도, 시간, 분위기에 따라 hole concentration ($7.4{\times}10^{16}cm^{-3}{\sim}6{\times}10^{17}cm^{-3}$), mobility(${\mu}h=\;1.72\;cm^2/V-s\;{\sim}15.2\;cm^2/V-s$), specific resistance(4.971 ohm-cm ~8.924 ohm-cm) 가 변화됨을 확인 할 수 있었다. 또한 광학적 특성을 분석하기 위해 Photoluminescence (PL)을 측정하였다.

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Effect of SiO2 Layer of Si Substrate on the Growth of Multiwall-Carbon Nanotubes (실리콘 기판의 산화층이 다중벽 탄소나노튜브 성장에 미치는 영향)

  • Kim, Geum-Chae;Lee, Soo-Kyoung;Kim, Sang-Hyo;Hwang, Sook-Hyun;Choi, Hyon-Kwang;Jeon, Min-Hyon
    • Korean Journal of Materials Research
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    • v.19 no.1
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    • pp.50-53
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    • 2009
  • Multi-walled carbon nanotubes (MWNTs) were synthesized on different substrates (bare Si and $SiO_2$/Si substrate) to investigate dye-sensitized solar cell (DSSC) applications as counter electrode materials. The synthesis of MWNTs samples used identical conditions of a Fe catalyst created by thermal chemical vapor deposition at $900^{\circ}C$. It was found that the diameter of the MWNTs on the Si substrate sample is approximately $5{\sim}10nm$ larger than that of a $SiO_2$/Si substrate sample. Moreover, MWNTs on a Si substrate sample were well-crystallized in terms of their Raman spectrum. In addition, the MWNTs on Si substrate sample show an enhanced redox reaction, as observed through a smaller interface resistance and faster reaction rates in the EIS spectrum. The results show that DSSCs with a MWNT counter electrode on a bare Si substrate sample demonstrate energy conversion efficiency in excess of 1.4 %.

Electrical characteristics of SiC thin film charge trap memory with barrier engineered tunnel layer

  • Han, Dong-Seok;Lee, Dong-Uk;Lee, Hyo-Jun;Kim, Eun-Kyu;You, Hee-Wook;Cho, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.255-255
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    • 2010
  • Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

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Frictional Anisotropy of CVD Bi-Layer Graphene Correlated with Surface Corrugated Structures

  • Park, Seonha;Choi, Mingi;Kim, Seokjun;Kim, Songkil
    • Tribology and Lubricants
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    • v.38 no.6
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    • pp.235-240
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    • 2022
  • Atomically-thin 2D nanomaterials can be easily deformed and have surface corrugations which can influence the frictional characteristics of the 2D nanomaterials. Chemical vapor deposition (CVD) graphene can be grown in a wafer scale, which is suitable as a large-area surface coating film. The CVD growth involves cooling process to room temperature, and the thermal expansion coefficients mismatch between graphene and the metallic substrate induces a compressive strain in graphene, resulting in the surface corrugations such as wrinkles and atomic ripples. Such corrugations can induce the friction anisotropy of graphene, and therefore, accurate imaging of the surface corrugation is significant for better understanding about the friction anisotropy of CVD graphene. In this work, the combinatorial analysis using friction force microscopy (FFM) and transverse shear microscopy (TSM) was implemented to unveil the friction anisotropy of CVD bi-layer graphene. The periodic friction anisotropy of the wrinkles was measured following a sinusoidal curve depending on the angles between the wrinkles and the scanning tip, and the two domains were observed to have the different friction signals due to the different directions of the atomic ripples, which was confirmed by the high-resolution FFM and TSM imaging. In addition, we revealed that the atomic ripples can be easily suppressed by ironing the surface during AFM scans with an appropriate normal force. This work demonstrates that the friction anisotropy of CVD bilayer graphene is well-correlated with the corrugated structures and the local friction anisotropy induced by the atomic ripples can be controllably removed by simple AFM scans.