• Title/Summary/Keyword: the property of multiplication

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Strain Decomposition Method in Hull Stress Monitoring System for Container Ship

  • Park, Jae-Woong;Kang, Yun-Tae
    • Journal of Ship and Ocean Technology
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    • v.7 no.3
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    • pp.56-65
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    • 2003
  • The hull monitoring systems of container ships with four long-base gages give enough information for identifying the hull girder loads such as bending and torsional moments. But such a load-identification for container ships has not been known. In this paper, a load-identification method is suggested in terms of a linear matrix equation that the measured strain vector equals to the multiplication of the transformation matrix and the desired strain component vector. The equation is proved to be mathematically complete by the property of positive-definite determinant of the transformation matrix. The method is applied to a hull stress monitoring system for 8100TED container ship during sea trial, and the estimated external loads illustrate reasonable results in comparison with the pre-estimated results. This moment decomposition concept has also been tested in real operation conditions. The typical phenomena over the Suez Canal illustrated very suitable results comparing with the physical understandings. Henceforth, one can effectively use the proposed concept to monitor the hull girder loads such as bending and torsional moments.

Block-based subband/DCT coding (블록단위 대역분할/DCT 부호화)

  • 김정권;이상욱;이충웅
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.2
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    • pp.97-105
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    • 1998
  • Subband/DCT coding has been introduced in order to transmit images of various resultions using one given image-codec, for nowadays there are various grades of quality in visual communication services. However, subband/DCT results in the increawse of multiplication number and memory size. In order to resolve this problem, we propose block-based subband/DCT coding in this paper. In block-based subband/DCT, the number of multiplications is not only reduced because we combine subband decomposistion with DCT, but the size of memory is also reduced because images can be parallel-processed block by block. We show that the number of multiplications is reduced, by analyzing the property ofblock-based subband/DCT matrix mathematically, and examine the performance of proposed coder, which adopts JPEG as backhand-coder after block-based subband/DCT.

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A Covariance Type ARMA Fast Transversal Filter (공분산형 ARMA 고속 Transversal 필터에 관한 연구)

  • Lee, Chul-Heui;Jang, Young-Soo
    • The Journal of the Acoustical Society of Korea
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    • v.11 no.1
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    • pp.67-79
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    • 1992
  • For effective on-line ARMA parameter estimation, a covariance type ARMA fast transversal filter (FTF) algorithm is presented. The proposed algorithm is a covariance type implementation of ELS(Extended Least Squares) estimator and it is a fast time update recursion which is based on the fact that the correlation matrix of ARMA model satisfies the shift invariance property in each sub-block. The geometric approach is used in the derivation of the proposed algorithm. It takes small computational burden of 13N+37 MADPR(Multiplication And Division Per Recursion). Also, AR and MA orders can be independetly and arbitrarily specified.

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OVERRINGS OF t-COPRIMELY PACKED DOMAINS

  • Kim, Hwan-Koo
    • Journal of the Korean Mathematical Society
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    • v.48 no.1
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    • pp.191-205
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    • 2011
  • It is well known that for a Krull domain R, the divisor class group of R is a torsion group if and only if every subintersection of R is a ring of quotients. Thus a natural question is that under what conditions, for a non-Krull domain R, every (t-)subintersection (resp., t-linked overring) of R is a ring of quotients or every (t-)subintersection (resp., t-linked overring) of R is at. To address this question, we introduce the notions of *-compact packedness and *-coprime packedness of (an ideal of) an integral domain R for a star operation * of finite character, mainly t or w. We also investigate the t-theoretic analogues of related results in the literature.

Implementation of Ternary Adder and Multiplier Using Current-Mode CMOS (전류모드 CMOS에 의한 3치 가산기 및 승산기의 구현)

  • Seong, Hyeon-Kyeong
    • Proceedings of the KIEE Conference
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    • 2006.10c
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    • pp.142-144
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    • 2006
  • In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

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A Correlation between Emile Sound and Other Waves (에밀레의 맥놀이와 다른 파동과의 상관관계)

  • 안정근;진용옥
    • The Journal of the Acoustical Society of Korea
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    • v.20 no.1
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    • pp.30-35
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    • 2001
  • The most important characteristic of Emile Bell's sound is a beating. It is modulation phenomenon which appears as a result of interference multiplication in time domain. This modulation phenomenon can be modeled as DSB-SC which suppress carrier and signals distributed both sides. The beatiog wave is observed in Laman distribution signal for polyvinyl speech signal, water vein wave, tide wave. The beating wave is caused by asymmetry Property of the bell.

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GALKIN'S LOWER BOUND CONJECURE FOR LAGRANGIAN AND ORTHOGONAL GRASSMANNIANS

  • Cheong, Daewoong;Han, Manwook
    • Bulletin of the Korean Mathematical Society
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    • v.57 no.4
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    • pp.933-943
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    • 2020
  • Let M be a Fano manifold, and H🟉(M; ℂ) be the quantum cohomology ring of M with the quantum product 🟉. For 𝜎 ∈ H🟉(M; ℂ), denote by [𝜎] the quantum multiplication operator 𝜎🟉 on H🟉(M; ℂ). It was conjectured several years ago [7,8] and has been proved for many Fano manifolds [1,2,10,14], including our cases, that the operator [c1(M)] has a real valued eigenvalue 𝛿0 which is maximal among eigenvalues of [c1(M)]. Galkin's lower bound conjecture [6] states that for a Fano manifold M, 𝛿0 ≥ dim M + 1, and the equality holds if and only if M is the projective space ℙn. In this note, we show that Galkin's lower bound conjecture holds for Lagrangian and orthogonal Grassmannians, modulo some exceptions for the equality.

Frame resizing scheme in H.264/AVC compressed domain (H.264/AVC 압축 도메인에서의 프레임 resizing 방법)

  • Oh, Hyung-Suk;Kim, Won-Ha
    • Proceedings of the KIEE Conference
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    • 2006.10c
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    • pp.145-147
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    • 2006
  • Image resizing is to change an image size by upsampling or downsampling of a digital image. Most still images and video frames are given in a compressed domain on digital media. Image resizing of a compressed image can be performed in a spatial domain via decompression or recompression. In general, resizing of a compressed image in a compressed domain is much faster than that in a spatial domain. In this paper, we propose an approach to resize images in the integer discrete cosine transform (DCT) domain, which exploits the multiplication-convolution property of DCT.

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A Study on Implementation of Multiple-Valued Arithmetic Processor using Current Mode CMOS (전류모드 CMOS에 의한 다치 연산기 구현에 관한 연구)

  • Seong, Hyeon-Kyeong;Yoon, Kwang-Sub
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.8
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    • pp.35-45
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    • 1999
  • In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

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On Fast M-Gold Hadamard Sequence Transform (고속 M-Gold-Hadamard 시퀀스 트랜스폼)

  • Lee, Mi-Sung;Lee, Moon-Ho;Park, Ju-Yong
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.7
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    • pp.93-101
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    • 2010
  • In this paper we generate Gold-sequence by using M-sequence which is made by two primitive polynomial of GF(2). Generally M-sequence is generated by linear feedback shift register code generator. Here we show that this matrix of appropriate permutation has Hadamard matrix property. This matrix proves that Gold-sequence through two M-sequence and additive matrix of one column has one of major properties of Hadamard matrix, orthogonal. and this matrix show another property that multiplication with one matrix and transpose matrix of this matrix have the result of unit matrix. Also M-sequence which is made by linear feedback shift register gets Hadamard matrix property mentioned above by adding matrices of one column and one row. And high-speed conversion is possible through L-matrix and the S-matrix.