• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.47-54
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• 2005

In this paper, a new synthesis method for testability of synchronous sequential circuits is suggested on an incompletely-specified state transition graph (STG) by reducing the number of redundant faults. In the suggested synthesis method, 1) a given STG is modified by adding undefined states and unspecified input transitions using distinguishable transition, 2) the STG is modified to be strongly-connected as much as possible. Experimental results with MCNC benchmark show that the number of redundant faults of gate-level circuits synthesized by our modified STGs are reduced, and much higher fault coverage is obtained.

• The Magazine of the IEIE
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• v.19 no.1
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• pp.65-70
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• 1992

• Journal of Internet Computing and Services
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• v.4 no.3
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• pp.31-37
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• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for finite state machine(FSM) is proposed. The proposed method always guarantees short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The efficiency of the proposed method is demonstrated using well-known MCNC'91 FSM benchmark circuits.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.3
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• pp.3-7
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• 2010

As the distance between signal lines in memories of high density ICs like SoCs decreases rapidly, failure occurs more frequently and effective memory test techniques are needed. In this paper, a new SRAM structure is proposed to decrease test complexity and test time for embedded DRAMs. In the presented technique, because memory test can be handled as a single port testing and read-write operation is possible at dual port without high complexity, test time can be much reduced.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.205-216
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• 1996

In this paper we propose an efficient robust path delay fault test genration algorithm for detection of path delay faluts in combinational ligic circuits. In the proposed robust test genration approach, the testability measure is computed for all gates in the circuit under test and these computed values are used to genrate weighted random delay test vetors for detection of path delay faults. For genrated robust test vectors, we perform fault simulation on ISCAS '85 benchmark circuits using parallel pattern technqieus. The results indicate that the proposed test genration method not only increases the number of detected robust path delay faults but also reduces the time taen to genrate robust tests.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1442-1447
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• 1990

In this paper we propose the search algorithm of the boundary nodes that defined as the circuit segmentation when CUT is tested by pseudo-exhaustive testing. The algorithm treats the testability values of the nodes in CUT as the population composed of teh raw data, and after examines the level of significance a and then estimate the confidence interval of teh testability values. Thus One can easily searched the c9oundary nodes and PO of sub circuits. The proposed algorithm has been implemented under UNIX OS with C-language, applied to the combinational logic CUT. As a result, it is shown that the pseudo-exhaustive test patterns are least generated when \ulcornerhas 0.786. We confirmed that the rate of test pattern is 1.22%, compared with exhaustive test.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.4
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• pp.3-10
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• 2011

To provide efficient keyword search on encrypted data, a public key encryption with keyword search (PEKS) was proposed by Boneh et al. A sender encrypts an e-mail and keywords with receiver's public key, respectively and uploads them on a server. Then a receiver generates a trapdoor of w with his secret key to search an e-mail related with some keyword w. However, Byun et al. showed that PEKS and some related schemes are not secure against keyword guessing attacks. In this paper, we propose a public key encryption with keyword search for restricted testability (PEKS-RT) scheme and show that our scheme is secure against keyword guessing attacks.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1998.10a
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• pp.268-268
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• 1998