• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.02a
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• pp.139-151
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• 2006

[ $\bullet$ ] 3D is proliferating in all package types $\bullet$ Thin packages challenge all assembly technologies $\bullet$ Package assembly and test are closely coupled and design for testability is imperative to success

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.91-98
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• 1992

In this paper, a new heuristic algorithm for designing combinational circuits suitable for verification testing is presented. The design method consists of argument reduction, input partitioning, output partitioning, and logic minimization. A new heuristic algorithm for input partitioning and output partitioning is developed and applied to designing combinational circuits to demonstrate its effectiveness.

• Proceedings of the CALSEC Conference
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• 2004.02a
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• pp.15-20
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• 2004

Positivism ▣Quantitative research ▣Descriptive, predictive, explanatory ▣Quest for university laws ▣Concerned with the empirical testability of theories (·Causal models (if it's not about cause-and-effect, it's not Science)) ▣Assumptions：(·Existence of a priori fixed relationship within phenomena ·Regular patterns of causation ·Independent from human mind(objective, factual)(omitted)

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.11
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• pp.94-104
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• 1995

In this paper, we present a new multi-level logic synthesis method for producing the multi-level circuits which can be easily tested by the pseudoexhaustive testing techniques. The method consists of four stages. In the first stage, it generates the minimum variable supports for each output of a multiple-output function. In the second stage, it removes the minimum variable supports which if used to implement the outputs, lead to inefficient pseudoexhaustive test. In the third stage, it determines the minimum variable support and logic (uncomplementary or complementary logic) for each output. In the fourth stage, it performs the multi-level logic synthesis so that each output. In the fourth stage, it performs the multi-level logic synthesis so that each output has the minimum variable support and logic determined in the third stage. To evaluate the performance and quality of the proposed method, we have experimented on the 56 benchmark examples. The results show that for 56 examples, our method obtains better results than MIS in terms of testability. Moreover, the method produces better results for 19 examples and the same results for 12 examples compared with MIS in terms of literal count although it has been developed to improve the testability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.286-292
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• 2012

Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.329-334
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• 2002

For the testability, this paper proposed the algorithm at autonomous synthesis which includes the data path structure as the self testing as possible on high level synthesis method when VHDL, coding is used in the system design area. In the proposed algorithm of this paper, MUXs and registers are assigned to the data path of designed system. And the designed data path could be mapped the H/W specification of described VHDL coding to the testable library. As a results, it was mapped H/W to the assign algorithm that is minimized MUX and the registers in collision graph.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.425-432
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• 1995

In this paper we propose a design and implementation technique of a universal automatic test pattern generator(UATPG) which is well suited for VLSI digital circuits. UATPG is designed to extend the capabilities of the existing APTG and to provide a convenient environment to computer-aided design(CAD) users. We employ heuristic techniques in line justification and fault propagation for functional gates during test pattern generation for a target fault. In addition, the flip-flops associated with design for testability (DFT) are exploited for pseudo PIs and pseudo POs to enhance the testabilities of VLSI circuits. As a result, UATPG shows a good enhancement in convenient usage and performance.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.31 no.3
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• pp.185-193
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• 2021

Objectives: Inhalation toxicity testing of chemical substances to identify carcinogenicity requires a long time and considerable cost, so the selection of test candidates is a very important aspect. This study was performed to determine optimal procedures for selecting carcinogenic inhalation toxicity test substances as conducted by the Occupational Safety and Health Research Institute (OSHRI). Methods: At the beginning, a database was constructed containing complex information such as usage amount, hazard, carcinogenicity prediction, and testability in order to select chemicals requiring carcinogenicity testing. Selection of test substances was carried out with priority given to usage, carcinogenicity, and testability. Results: Chemicals used in large quantities in industrial fields and strongly suspected of carcinogenicity were winnowed down to 12 substances, and these substances were scheduled for future testing by OSHRI. Conclusions: For the stable and reliable operation of carcinogenicity tests as conducted by OSHRI, this study standardized the procedures for selecting carcinogenicity test substances and suggested the introduction of various carcinogenicity prediction techniques.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.37-43
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• 1999

Modules of the system that requires large capacity and high-speed information processing are implemented in the form of MCM that allows high-speed data processing, high density circuit integration and widely applied to such fields as ATM, GPS and PCS. Hence we developed the ATM switching module that is consisted of three chips and 2.48 Gbps data throughput, in the form of 10 multi-layer by Cu/Photo-BCB and 491pin PBGA which size is $48 \times 48 \textrm {mm}^2$. hnologies required for the development of the MCM includes extracting parameters for designing the substrate/package through the interconnect characterization to implement the high-speed characteristics, thermal management at the high-density MCM, and the generation of the testability that is one of the most difficult issues for developing the MCM. For the development of the ATM Switching MCM, we extracted signaling delay, via characteristics and crosstalk parameters through the interconnect characterization on the MCM-D. For the thermal management of 15.6 Watt under the high-density structure, we carried out the thermal analysis. formed 1.108 thermal vias through the substrate, and performed heat-proofing processing for the entire package so that it can keep the temperature less than $85^{\circ}C$. Lastly, in order to ensure the testability, we verified the substrate through fine pitch probing and applied the Boundary Scan Test (BST) for verifying the complex packaging/assembling processes, through which we developed an efficient and cost-effective product.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.685-691
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• 2001

본 논문은 4단계 파이프 라인과 VLIW (Very Long Instruction Word) 구조를 갖는 FLOVA라는 DSP 프로세서의 테스트용이 설계 기법을 다룬다. Full-scan design, BIST(Built-In-Self-Test), IEEE 1149.1의 기법들이 플립플롭과 floaing point unit, 내장된 메모리, I/O cell 등에 각각 적용되었다. 이러한 기법들은 테스트 용이도의 관점에서 FLOVA의 구조에 적절하게 적용되었다. 본 논문에서는 이와 같이 FLOVA에 적용된 테스트 용이 설계의 특징들을 중심으로 상세하게 기술한다.