• Transactions of the Korean Society of Mechanical Engineers B
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• v.34 no.9
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• pp.867-873
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• 2010

The failure of water-cooled generator stator windings as a result of insulation breakdown due to coolant water leaks and water absorption often occurs worldwide. Such failure can cause severe grid-related accidents as well as huge economic losses. More than 50% of domestic generators have been operated for over 15 years, and therefore, they exhibit signs of aging. Leaking and water-absorbing windings are often found during an overhaul. In an existing method for evaluating the integrity of generator stator windings, the drying process of the interior of the windings is ignored and only final leak tests are performed. In this study, it is shown that water leaks and water absorption in stator windings can be detected indirectly through vacuum pattern analysis in the vacuum drying mode, which is the used in the preparation stage of the leak test.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1503-1506
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• 1987

This paper proposes the self test method for 16 point FFT processor with systolic array architecture. To test efficiently and solve the increased hardware problems due to built-in self test, we change the normal registers into Linear Feedback Shift Registers(LFSR). LFSR can be served as a test pattern generator or a signature analyzer during self test operation, while LFSR a ordering register or a accumulator during normal operation. From the results of logic simulation for 16 point FFT processor by YSLOG, the total time is estimated in about. 21.4 [us].

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.365-368
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• 2002

WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NMI ion implantation and deposition & etch nitride layer New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.486-495
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• 2009

This paper proposes a new methodology on reliability evaluation of a power system including solar cell generators (SCG). The SCGs using renewable energy resource such as solar radiation(SR) should be modeled as multi-state operational model because the uncertainty of the resource supply may occur an effect as same as the forced outage of generator in viewpoint of adequacy reliability of system. While a two-state model is well suited for modeling conventional generators, a multi-state model is needed to model the SCGs due to the random variation of solar radiation. This makes the method of calculating reliability evaluation indices of the SCG different from the conventional generator. After identifying the typical pattern of the SR probability distribution function(pdf) from SR actual data, this paper describes modelling, methodology and details process for reliability evaluation of the solar cell generators integrated with power system. Two test results indicate the viability of the proposed method.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1931_1933
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• 2009

NoC 기반 시스템이 적용되는 설계는 시스템 크기가 커짐에 따라 칩 테스트 문제도 동시에 제기 되고 있다. 이에 따라 NoC 기반의 시스템의 테스트 시간을 줄일 수 있는 internal test 방식의 새로운 BIST(Built-in Self-Test) 구조에 관한 연구를 하였다. 기존의 NoC 기반 시스템의 BIST 테스트 구조는 각각의 router와 core에 BIST logic과 random pattern generator로 LFSR(Linear Feedback Shift Register)을 사용하여 연결하는 individual 방식과 하나의 BIST logic과 LFSR을 사용하여 각각의 router와 core에 병렬로 연결하는 distributed 방식을 사용한다. 이때, LFSR에서 생성된 테스트 벡터가 router에 사용되는 FIFO 메모리를 통과하면서 생기는 테스트 타임 증가를 줄이기 위하여 shift register 형태의 FIFO 메모리를 변경하였다 제안된 방법에서 테스트 커버리지 98%이상을 달성하였고, area overhead면에서 효과를 볼 수 있다.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.27-30
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• 2003

The recent technology developments introduce new difficulties into the test process by the increased complexity of the chip. Most widely used method for testing high complexity and embedded systems is built-in self-test(BIST). In this paper, we describe 5-stage pipeline system as circuit under testing(CUT) and proposed a BIST scheme for the hazard detection unit of the pipeline system. The proposed BIST scheme can generate sequential instruction sets by pseudo-random pattern generator that can detect all hazard issues and compare the expected hazard signals with those of the pipelined system. Although BIST schemes require additional area in the system, it proves to provide a low-cost test solution and significantly reduce the test time.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.5
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• pp.231-236
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• 2008

This paper proposes a cost-efficient and flexible FPGA-based logic circuit emulation platform. By improving the performance and adding more features, this new platform is an enhanced version of our LAPG. It consists of an FPGA-based hardware engine and software element to drive the emulation and monitor the results. It also provides an interactive verification environment which uses an efficient communication protocol through a bi-directional serial link between the host and the FPGA board. The experimental results show that this new approach saves $55%{\sim}99%$ of communication overhead compared with other methods. According to the test results, the new LAPG is more area efficient in complex circuits with many I/O ports.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2017.05a
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• pp.637-642
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• 2017

In this study, cold flow and combustion tests are conducted and analyzed to validate designed rocket engine head generating high temperature/pressure steam. At first, uni-injector was designed and manufactured, and cold flow test was conducted. Through this, differential pressure that can supply designed flow rate was confirmed. Also, Each injector's spray pattern were confirmed by patternator. Based on cold flow test results, we selected injectors among the candidates and arranged them on engine head, and cold flow and propellant spray tests were conducted. Finally, combustion test was carried out to analyze the flow rate, pressure, combustion efficiency. As a result, validation of rocket engine head for the development of the high temperature and high pressure steam generator has been completed.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.425-432
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• 1995

In this paper we propose a design and implementation technique of a universal automatic test pattern generator(UATPG) which is well suited for VLSI digital circuits. UATPG is designed to extend the capabilities of the existing APTG and to provide a convenient environment to computer-aided design(CAD) users. We employ heuristic techniques in line justification and fault propagation for functional gates during test pattern generation for a target fault. In addition, the flip-flops associated with design for testability (DFT) are exploited for pseudo PIs and pseudo POs to enhance the testabilities of VLSI circuits. As a result, UATPG shows a good enhancement in convenient usage and performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.85-97
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• 2002

STUMPS has been widely used for built-in self-test of scan design with multiple scan chains. In the STUMPS architecture, there is very high correlation between the bit sequences in the adjacent scan chains. This correlation causes circuits lower the fault coverage. In order to solve this problem, an extra combinational circuit block(phase shifter) is placed between the LFSR and the inputs of STUMPS architecture despite the hardware overhead increase. This paper introduces an efficient test pattern generation technique and built-in self-test architecture for sequential circuits with multiple scan chains. The proposed test pattern generator is not used the input of LFSR and phase shifter, hence hardware overhead can be reduced and sufficiently high fault coverage is obtained. Only several XOR gates in each scan chain are required to modify the circuit for the scan BIST, so that the design is very simple.