Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1987.07b
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- Pages.1503-1506
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- 1987
Self-Testing for FFT processor with systolic array architecture
시스토릭 어레이 구조를 갖는 FFT 프로세서에 대한 Self-Testing
- Lee, J.K. (Dept. of Electronics Engineering, Yonsei Univ.) ;
- Kang, B.H. (Dept. of Electronics Engineering, Yonsei Univ.) ;
- Choi, B.I. (Dept. of Electronics Engineering, Yonsei Univ.) ;
- Shin, K.U. (Dept. of Electronics Engineering, Yonsei Univ.) ;
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Lee, M.K.
(Dept. of Electronics Engineering, Yonsei Univ.)
- Published : 1987.07.03
Abstract
This paper proposes the self test method for 16 point FFT processor with systolic array architecture. To test efficiently and solve the increased hardware problems due to built-in self test, we change the normal registers into Linear Feedback Shift Registers(LFSR). LFSR can be served as a test pattern generator or a signature analyzer during self test operation, while LFSR a ordering register or a accumulator during normal operation. From the results of logic simulation for 16 point FFT processor by YSLOG, the total time is estimated in about. 21.4 [us].
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