• Proceedings of the KIEE Conference
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• 1999.07a
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• pp.271-273
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• 1999

In this paper 30 kVA Super-Conducting Generator's test and analysis results of OCC and SCC are presented. Also the test and FE analysis results of the generator under 1.2, 2.4, and 3.6[kW] load are described. For FE analysis of the generator's performance, the external circuit is coupled with the FE region. The generator's end winding reactance is obtained based on the design data, actual dimension, preliminary FE analysis, and empirical formulas. The comparison of FE analysis coupled with external circuit to the test results shows a good agreement.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.343-344
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• 2017

본 논문은 HVDC컨버터의 사이리스터 밸브 시험용 STC(Synthetic Test Circuit)의 전류원 특성을 개선하기 위한 제어기법을 제안한다. 기존의 저전압-대전류 회로의 보조스위치를 이용하여 사이리스터 밸브의 턴-오프 시 전류 하강 시간을 턴-온 시 전류 상승 시간과 유사하게 제어한다. 제안하는 기법에 대해 설명하고, 시뮬레이션을 통해 제안하는 기법의 타당성을 검증하였다.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.6-8
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• 1993

In this paper, we proposed a new method which does not need no load test for the characteristics analysis of linear induction motor. A new equivalent circuit of LIM is chosen and a method of determining its constants from results of the lock test is discussed. The calculated results were satisfactorily agreed with experimental results and conventional method.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.540-542
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• 1993

In this paper, we proposed a new method which does not need no load test for the characteristics analysis of linear induction motor. A new equivalent circuit of LIM is chosen and a method of determining its constants from results of the lock test is discussed. The calculated results were satisfactorily agreed with experimental results and conventional method.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.196-198
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• 2020

본 논문은 SiC MOSFET의 단락 검출을 위한 고정밀 Rogowski 코일 회로 설계 방법을 제안한다. 설계 방법을 제안하기 위해 먼저 Rogowski 코일의 기본 구성인 적분기를 실제 시스템 요구 사양에 맞추어 설계한다. 설계한 회로의 성능 확인을 위하여 DPT (double pulse test)를 실시하며, test 결과 분석을 통해 문제점을 파악하고 전류 센싱 정밀도 향상을 위해 입출력 필터 설계 및 Rogowski 코일 턴 수를 변경한다. 변경한 각 조건들에 대하여 DPT를 진행하고 각 test 결과를 기반으로 Rogowski 코일 회로 설계 방안을 제안한다.

• PNF and Movement
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• v.8 no.2
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• pp.47-55
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• 2010

Purpose : The purpose of present study was to determine effects of a task-oriented circuit training(TOCT) for lower limb on walking ability after stroke. Methods : Twenty one chronic stroke patients participated. Participants were randomly divided into either TOCT group or control group(11 experimental, 10 control). All of participants were in-patients at local rehabilitation centre and had been receiving a traditional rehabilitation program, five days a week. TOCT group have additionally undergone for four weeks, three days a week, the TOCT program but control group was not received any additional program except the traditional rehabilitation program. The 10 m walking test (10MWT), the 2 min walking test (2MWT), the step test (ST) and the figure-8 walking test (F8WT) to measure a walking ability were carried out twice before and after training. Results : After participation in the program, subjects of TOCT demonstrated a significant improvement in the scores of the 10MWT, 2MWT, the ST, the F8WT. The control group had no change on the any tests. After the training, the results to improve significantly in TOCT group compared to post-test of control group were the time of 10MWT and the time and the step of curved walking of F8WT. Conclusion : The present study suggests that the TOCT program may become a useful strategy for enhancing walking ability in the rehabilitation of stroke patients.

• ETRI Journal
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• v.19 no.2
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• pp.35-47
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• 1997

A power amplifier operating at 3.3 V has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESF from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than -26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be -33 dBc at a high output power of 26 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.401-410
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• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.89-90
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• 2013

Higher power density, higher operational temperature, lower on state resistance and higher switching frequency capabilities of Silicon Carbide (SiC) technology devices compared to Silicon (Si) devices makes it has higher promising market. One of the most developed SiC devices is the power MOSFET. This study tests the SiC MOSFET under short circuit conditions taking into account the effect of gate voltage characteristics. The results will be compared to IGBT and MOSFET Si devices with similar ratings. A tester circuit was designed to perform the short circuit operation.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.7-13
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• 2001

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently. IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. This paper presents a new BIC for the internal current test in CMOS logic circuit. Our circuit is composed of Magnetoresistive current sensor, level shifter, comparator, reference voltage circuit and a circuit be IDDQ tested as a kind of self-testing fashion by using the proposed BIC.