• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2011년도 한국컴퓨터종합학술대회논문집 Vol.38 No.1(B)
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• pp.313-316
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• 2011

SRAM-based FPGAs are very sensitive to single event upset(SEU) induced by space irradiation. To mitigate SEU effects, space applications employ some mitigation schemes. The triple modular redundancy(TMR) is a well-known mitigation scheme. It uses one or three voters as well as three identical blocks performing the same work. The voters can mask out one error in the outputs from the three replicated blocks. One SEU error in TMRed circuits can be masked but it needs to be detected for some reasons such as to analyze the SEU effects in the satellite or to recover the circuits from the error before additional error occur. In this paper, we developed a fault detection circuit and reporting system to detect a fault on the TMRed circuits. To verify our error detection circuit and reporting circuit, we performed an irradiation test at MC-50 Cyclotron. Experimental results showed that error detection circuit can detect a fault on the TMRed test circuit in radiation environment.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.314-315
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• 2011

This paper introduces the design and control method of braking chopper circuit which can supply input power to ventilation inverter of traction control system. The DC input voltage from auxiliary block (static inverter) is normally used as an input of ventilation inverter. It converts DC input to AC output voltage to drive cooling fans for traction control system and traction motors. The electrical braking force is very important for high speed train to guarantee safety even though the train is running in the dead section where the pantograph voltage is not supplied. When the high speed train decelerate speed in dead section, the regenerative energy is dissipated by braking resistor. This paper proposed the braking chopper control method to implement rheostatic braking function and the appropriate chopper circuit for supplying voltage source to ventilation inverter during rheostatic braking mode. The proposed chopper circuit makes it possible for traction control system to regenerate power continuously regardless of the existence of pantograph voltage. The feasibility of proposed braking chopper control and circuit were proven by inertia load test and actual train field test.

• 한국산학기술학회논문지
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• 제4권3호
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• pp.177-182
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• 2003

Flash memory는 device 특성상 peripheral circuit을 구성하는 transistor의 종류가 다양하고, 이에 따른 각 transistor의 동작 전압 영역이 넓다. 이에 따라 설계 초기의 전기적 특성 사양 결정을 위해서는, 실리콘상에서 소자의 scale down에 따른 전기적 특성을 선 검증하는 과정이 필수적이었으며, 이로 인해 설계 및 소자 개발의 기간을 단축하기 어려웠다. 본 연구에서는 TCAD tool을 사용하여 실리콘상에서의 제작 공정을 거치지 않고, 효과적으로 model parameter를 생성할 수 있도록 하는 방법을 제안하여 전기적 특성 사양 결정과 설계 단계의 시간 지연을 감소할 수 있도록 한다. 또한 성공적 TCAD tool적용을 위해 필요한 process/device simulator의 calibration methodology와 이를 flash 메모리 소자에 대해 적용 검증한 결과를 분석한다.

• 한국초전도ㆍ저온공학회논문지
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• 제14권3호
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• pp.13-17
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• 2012

KEPCO Research Institute has been researching a Superconducting Fault Current Limiter (SFCL) which is considered one of solutions of fault current problems with Korea Institute of Machinery & Materials (KIMM) and Hanyang University since 2011. In this paper, we fabricated a current limiting module and conducted electrical short circuit tests for checking the validity of the transmission level SFCL design. Based on the short circuit characteristics of the second generation High Temperature Superconductor (HTS), we analyzed the short circuit characteristics of 3 parallel connected superconducting wires. The structure of the HTS wire is as follows: the stainless steel stabilizer of $100{\mu}m$ is laminated on the superconductor layer and under the substrate, both of which are electrically jointed with solder. We fabricated the current limiting module which has 40 series and 6 parallel connections and studied the short circuit characteristics of the module under various voltage levels.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제3B권4호
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• pp.165-172
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• 2003

Low voltage circuit breakers are widely used in power distribution systems to interrupt fault current rapidly and to assure the reliability of the power supply. This paper is focused on understanding the interrupting capability, more specifically of the contacts and the arc runner, based on the shape of the contact system in the current molded case circuit breaker (hereafter MCCB). Moreover, in order to improve the interrupting capability of the circuit breaker, the estimation and analysis of the interrupting capability, based on the 3-D magnetic flux analysis, were developed. Furthermore, this paper also presents results of the estimation and analysis of the interrupting capability when applied to different model breakers. In addition, this paper analyzes the efficiency of the interrupting tests by forming false current paths consisting of a three-division cascade arc runner in the contact system. With regards to the interrupting test, there is a need to assure that the optimum design required to analyze the electromagnetic forces of the contact system generated by the current and flux density be present. Based on the results of this study, this paper presents both computational analysis and test results for the newly developed MCCB 460V/225A/50㎄ contact system.

• 대한방사선기술학회지:방사선기술과학
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• 제35권4호
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• pp.315-319
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• 2012

본 연구는 위치 민감형 광 증폭 다이오드로부터 나오는 신호를 증폭 및 파형 변화 후 신호의 크기를 검출하여 일정시간 동안 유지시키는 뒷단 회로 개발에 관한 연구이다. 신호발생기에서 발생한 소신호를 증폭 소자를 통한 안정적인 증폭 후 미분회로를 통하여 신호 파형을 검출하기 수월한 형태로 변형 하고, peak/hold 회로에서 피크의 최대점을 일정시간 유지하여 신호의 수집을 원활하게 하였다. 본 회로에 대한 독립적인 성능 평가를 위하여 상용 장비로부터의 검사신호를 입력으로 사용하였다.

• Journal of Electrical Engineering and Technology
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• 제13권2호
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• pp.875-880
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• 2018

This paper proposes a novel combined compensation structure in the infrared receiver chip. For the infrared communication chip, the current-voltage (I-V) convert circuit is crucial and important. The circuit is composed by the transimpedance amplifier (TIA) and the combined compensation structures. The TIA converts the incited photons into photocurrent. In order to amplify the photocurrent and avoid the saturation, the TIA uses the combined compensation circuit. This novel compensation structure has the low frequency compensation and high frequency compensation circuit. The low frequency compensation circuit rejects the low frequency photocurrent in the ambient light preventing the saturation. The high frequency compensation circuit raises the high frequency input impedance preserving the sensitivity to the signal of interest. This circuit was implemented in a $0.6{\mu}m$ BiCMOS process. Simulation of the proposed circuit is carried out in the Cadence software, with the 3V power supply, it achieves a low frequency photocurrent rejection and the gain keeps 109dB ranging from 10nA to $300{\mu}A$. The test result fits the simulation and all the results exploit the validity of the circuit.

• 전력전자학회논문지
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• 제26권3호
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• pp.176-182
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• 2021

This research proposes a high-frequency circuit that can accurately predict the differential mode noise of single-phase inverters at the circuit design stage. Proposed single-phase inverter high frequency circuit in the work is a form in which harmonic impedance components are added to the basic single-phase inverter circuit configuration. For accurate noise prediction, parasitic components present in each part of the differential noise path were extracted. Impedance was extracted using a network analyzer and Q3D in the measurement range of 150 kHz to 30 MHz. A high-frequency circuit model was completed by applying the measured values. Simulations and experiments were conducted to confirm the validity of the high-frequency circuit. As a result, we were able to predict the resonance point of the differential mode voltage extracted as an experimental value with a high-frequency circuit model within an approximately 10% error. Through this outcome, we could verify that differential mode noise can be accurately predicted using the proposed model of the high-frequency circuit without a separate test bench for noise measurement.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.507-510
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• 1998

In this paper, a novel test method is proposed to detect hard and soft fault in CMOS operational amplifiers. Proposed test method mark use of the offset character, which is one of the op-amps characteristics. During the test mode, CUT is implemented to unit gain op-amps with feedback loop. When the input is grounded, a good circuit has a small offset voltage, but a faulty circuit has a large offset voltage exceeding predefined range of tolerance. Using the proposed method, no test vector is required to be applied. Therefore the test vector generation problem is eliminated and the test time is reduced. The accuracy and effectiveness of the method is verified through HSPICE simulation.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 추계학술대회 논문집
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• pp.459-462
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• 2002

This paper presents the development or a keypad test system for the improvement or the working environment and productivity improvement using the microprocessor PIC16F877 Chip. In order to detect the fault of keypad products, the design of hardware and software is performed in this system. All controls of the system is implemented by the 8 bit one chip micro-controller PIC. This keypad test system can also recognizes the work process, the work result and the fault position of the keypad which is made by the method of a flexible printed circuit (FPC) and construct the database about test results using personal computer. The experimental results show the effective performance of the keypad test system.