• The Pure and Applied Mathematics
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• v.20 no.2
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• pp.129-136
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• 2013

We research properties of ternary numbers with values in ${\Lambda}(2)$. Also, we represent dual ternary numbers in the sense of Clifford algebras of real six dimensional spaces. We give generation theorems in dual ternary number systems in view of Clifford analysis, and obtain Cauchy theorems with respect to dual ternary numbers.

• Honam Mathematical Journal
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• v.38 no.4
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• pp.685-692
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• 2016

The aim of this paper is to investigate the differentials of the hypercomplex valued functions in Clifford analysis. Like as the differentials defined by the naïve approach in one complex variable analysis, we define the differentials of functions with values in ternary number functions by same ways. And we survey the properties of each differential with respect to a non-commutativity of the skew field.

• Journal of the Korean Mathematical Society
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• v.56 no.1
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• pp.67-80
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• 2019

For positive integers a, b, c, and an integer n, the number of integer solutions $(x,y,z){\in}{\mathbb{Z}}^3$ of $a{\frac{x(x-1)}{2}}+b{\frac{y(y-1)}{2}}+c{\frac{z(z-1)}{2}}=n$ is denoted by t(a, b, c; n). In this article, we prove some relations between t(a, b, c; n) and the numbers of representations of integers by some ternary quadratic forms. In particular, we prove various conjectures given by Z. H. Sun in [6].

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.6
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• pp.568-572
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• 2009

We present a ternary microfluidic multiplexer unit, capable to address three flow channels using a pair of control lines with two different threshold pressure valves. The previous binary multiplexer unit addresses only two flow channels using a pair of control line with identical threshold pressure valves, thus addressing $2^{n/2}$ flow channels using n control lines. The present ternary multiplexer addressing three flow channels using a pair of control lines, however, is capable to address $3^{n/2}$ flow channels using n control lines with two different threshold pressure valves. In the experimental study, we characterized the threshold pressure and the response time of the valves used in the ternary multiplexer. From the experimental observation, we also verified that the present ternary multiplexer unit could be operated by two equivalent valve operating conditions: the different static pressures and dynamic pressures at different duty ratio. And then, $3{\times}3$ well array stacking ternary multiplexers in serial is addressed in cross and plus patterns, thus demonstrating the individual flow channel addressing capability of the ternary multiplexer. Thus, the present ternary multiplexer reduces the number of control lines for addressing flow channels, achieving the high well control efficiency required for simple and compact microfluidic systems.

• East Asian mathematical journal
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• v.29 no.3
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• pp.293-302
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• 2013

We research properties of ternary numbers and hyperholomorphic functions with values in $\mathbb{C}$(2). We represent reduced quaternion numbers and obtain some propertries in dual reduced quaternion systems in view of Clifford analysis. Moreover, we obtain Cauchy theorems with respect to dual reduced quaternions.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.57-63
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• 1994

The logic function synthesis using ULM U$_h$ is constructed based on canonic Reed-Muller expansion coefficient for a given function. This paper proposes the fast synthesis algorithm using ULM U$_h$ for ternary function. By using circuit cost and synthesis method of proposed in this paper, order of control input variable minimum number of ULM U$_h$ can be decided in the synthesis of n-variable ternary function. Accordingly, this method enables to optimum circuit realization for ternary function synthesis using ULM ULM U$_h$ and can be applied to ternary function synthesis using ULM U$_h$. The complexity of search for select the order of all control input variables is (n+2)(n-1)/2.

• 전기의세계
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• v.28 no.1
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• pp.43-52
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• 1979

Recently, interest in multivalued(MV) logic system has been increased, despites the apparent difficulties for practical application. This is because of the many advantages of the MV compared with the 2-valued logic systems, such as; (a) higher speed of arithmetical operation on account of the smaller number of digits required for a given data, (b) better utilization of data transmission channels on account of the higher information contents per line, (c) potentially higher density of information storage. This paper describes a MV switching theory and experimental MV logic elements based on current-mode logic technique. These elements tried were a 3-stable pulse generator, a ternary AND, a ternary OR, a MT circuit and a ternary inverter. Tristable flops which are indispensable for constituting a ternary shift register are synthesized using these gates. A BCD to TCD decoder, and vice versa, are proposed by using a ternary inverter and some binary gates. Thus, the feasibility of a large scale MV digital system has been demonstrate.

• Macromolecular Research
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• v.11 no.5
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• pp.303-310
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• 2003

The phase behavior of binary blends of dimethylpolycarbonate-tetramethyl polycarbonate (DMPCTMPC) copolycarbonates and styrene-acrylonitrile (SAN) copolymers has been examined and then compared with that of DMPC/TMPC/SAN ternary blends having the same chemical components and compositions except that the DMPC and TMPC were present in the form of homopolymers. Both binary and ternary blends were miscible at certain blends compositions, and the miscible blends showed the LCST-type phase behavior or did not phase separated until thermal degradation temperature. The miscible region of binary blends is wider than that of the corresponding ternary blends. Furthermore, the phase-separation temperatures of miscible binary blends are higher than those of miscible ternary blends at the same chemical compositions. To explain the destabilization of polymer mixture with the increase of the number of component, interaction energies of binary pairs involved in these blends were calculated from the phase separation temperatures using lattice-fluid theory and then the phase stability conditions for the polymer mixture was analyzed with volume fluctuation thermodynamics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.491-499
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• 2007

In this paper, we present a design method of the ternary logic circuits based on Reed-Muller expansions. The design method of the presented ternary logic circuits checks the degree of each variable for the coefficients of Reed-Holler Expansions(RME) and determines the order of optimal control input variables that minimize the number of Reed-Muller Expansions modules. The order of optimal control input variables is utilized the computation of circuit cost matrix. The ternary logic circuits of the minimized tree structures to be constructed by RME modules based on Reed-Muller Expansions are realized using the computation results of its circuit cost matrix. This method is only performed under unit time in order to search for the optimal control input variables. Also, this method is able to be programmed by computer and the run time on programming is $3^n$.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.152-157
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• 2024

In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTI and NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic '0' or '2,' the proposed SRAM cell operates the same way as conventional binary SRAM. For logic '1,' it works differently as storage nodes on each side retain voltages of V_DD/2 and V_DD, respectively, using the subthreshold current of two additional transistors. By applying the ternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and the proposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in static power consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of the cell operation when V_DD is set to 0.9 V.