• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권4호
• /
• pp.215-220
• /
• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• International Journal of CAD/CAM
• /
• 제8권1호
• /
• pp.29-36
• /
• 2009

Domain mapping is a bijective transformation of one domain to another, usually from a complicated general domain to a chosen convex domain. This is directly useful in many application problems like shape modeling, morphing, texture mapping, shape matching, remeshing, path planning etc. A new approach considering the domain as made up of structural elements, like membranes or trusses, is developed and implemented using the nonlinear finite element formulation. The mapping is performed in two stages, boundary mapping and inside mapping. The boundary of the 3-D domain is mapped to the surface of a convex domain (in this case, a sphere) in the first stage and then the displacement/distortion of this boundary is used as boundary conditions for mapping the interior of the domain in the second stage. This is a general method and it develops a bijective mapping in all cases with judicious choice of material properties and finite element analysis. The consistent global parameterization produced by this method for an arbitrary genus zero closed surface is useful in shape modeling. Results are convincing to accept this finite element structural approach for domain mapping as a good method for many purposes.

• Journal of information and communication convergence engineering
• /
• 제5권2호
• /
• pp.131-135
• /
• 2007

In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Journal of information and communication convergence engineering
• /
• 제5권1호
• /
• pp.59-63
• /
• 2007

In this paper, a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• 전자공학회논문지A
• /
• 제29A권2호
• /
• pp.88-99
• /
• 1992

This paper presents an efficient method of mapping Boolean equations to a set of library gates. The proposed system performs technology mapping by graph covering. To select optimal area cover, a new cost function and local area optimization are proposed. Experimental results show that the proposed algorithm produces effective mapping using given library.

• 반도체디스플레이기술학회지
• /
• 제20권2호
• /
• pp.137-140
• /
• 2021

High dynamic range (HDR) technology has been drawing attention in the field of imaging and consumer entertainment. As tools for capturing and creating HDR contents, encoding, and transmission evolve to support HDR formats, various display capabilities are being developed and increased. Hence, there is need for remapping native HDR imagery for display on lower quality legacy standard dynamic range (SDR) displays. This operation is referred to as tone mapping. In this paper, we present a sectional tone mapping method by Lenzen, and expand upon a tone mapping approach to improve temporal stability while maintaining picture quality. Compared to the existing block-based sectional tone mapping, our method uses the edge awareness-based tone mapping. We estimate the performance of the objective metric on temporal flickering. The experimental result shows that the algorithm maintains a smoother relationship between the output luminance values, and this reveals success in reducing halos and improving temporal stability with adopted edge aware filtering.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년도 추계학술대회 논문집 전력기술부문
• /
• pp.3-5
• /
• 2006

IEC 61850 기반의 변전소 자동화용 IED를 구현함에 있어서 IEC 61850 통신을 위한 IED의 통신부와 계전기능을 위한 보호계전부의 mapping은 중요한 부분이다. 물론 통신부와 보호계를 통합하여 구성할 수도 있지만 통신부와 보호계전부가 분리된 형태의 IED에서는 데이터 mapping의 방법이 필요하다. 보호계전부와 통신부가 분리된 토B의 경우, 보호계선 데이터를 IEC 61850데이터 형으로 적용하기 위해서는 데이터 형의 변화와 데이터의 연산 과정등의 mapping이 필요하다. 본 논문에서는 IEC 61850에서 표준으로 제시하는 CID(Configured IED Description)파일을 이용하여 보호계전부와 IEC 61850 통신부 사이의 데이터들의 mapping 방법과 동적 연산 방법을 제시하고 제시된 방법에 따른 결과물을 보여준다.

• 센서학회지
• /
• 제26권1호
• /
• pp.24-27
• /
• 2017

In this study, I developed a simple and low cost process-printing a silver, carbon, dielectric, adhesive layer on PET films using screen printing technology and bonding the two films face-to-face-to fabricate a low price capacitive pressure-mapping sensor. Both electrodes forming the pressure measuring capacitor are arranged between the two PET films similar to a sandwich. Therefore, the sensor has the advantage of minimizing the influence of external noise. In this study, a $10{\times}10$ capacitance-type pressure-mapping sensor was fabricated and its characteristics were analyzed.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
• /
• pp.1165-1168
• /
• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.

• 대한전자공학회논문지SD
• /
• 제39권8호
• /
• pp.84-91
• /
• 2002

In this paper, we proposed a CLB-based CPLD technology mapping algorithm for power minimization under time constraint in combinational circuit. The main idea of our algorithm is to exploit the "cut enumeration and feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. In our technology mapping algorithm conducted a low power by calculating TD and EP of each node and decomposing them on the circuit composed of DAG. It also takes the number of input, output, and OR-term into account on condition that mapping can be done up to the base of CLB, and so it generates the feasible clusters to meet the condition of time constraint. Of the feasible clusters, we should first be mapping the one that h3s the least output for technology mapping of power minimization and choose to map the other to meet the condition of time constraint afterwards. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the exiting algorithms. The experimental results show that our approach is shown a decrease of 46.79% compared with DDMAP and that of 24.38% for TEMPLA in the power consumption.