Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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CLB-Based CPLD Technology Mapping Algorithm for Power Minimization under Time Constraint

시간 제약 조건 하에서 저전력을 고려한 CLB구조의 CPLD 기술 매핑 알고리즘

  • 김재진 (극동정보대학 전산정보처리과) ;
  • 김희석 (청주대학교 정보통신공학부)
  • Published : 2002.08.01
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Abstract

In this paper, we proposed a CLB-based CPLD technology mapping algorithm for power minimization under time constraint in combinational circuit. The main idea of our algorithm is to exploit the "cut enumeration and feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. In our technology mapping algorithm conducted a low power by calculating TD and EP of each node and decomposing them on the circuit composed of DAG. It also takes the number of input, output, and OR-term into account on condition that mapping can be done up to the base of CLB, and so it generates the feasible clusters to meet the condition of time constraint. Of the feasible clusters, we should first be mapping the one that h3s the least output for technology mapping of power minimization and choose to map the other to meet the condition of time constraint afterwards. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the exiting algorithms. The experimental results show that our approach is shown a decrease of 46.79% compared with DDMAP and that of 24.38% for TEMPLA in the power consumption.

Keywords

References

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