• 한국통신학회논문지
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• 제21권2호
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• pp.313-325
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• 1996

This paper presents a new architecture for full-search block-matching motion estimation. The architecture is based on linear systolic arrays. High speed operation is obtained by feeding reference data, search data, and control signals into the linear systolic array in a pipelined fashion. Input data are fed into the linear systolic array at a half of the processor speed, reducing the required data bandwidth to half. The proposed architecture has a good scalability with respect to the number of processors and input bandwidth when the size of reference block and search range change.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.787-790
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• 2003

This paper describes a high speed correlator that can acquire synchronization quickly. The existing addition algorithm is a binary adder tree architecture that will result in extremely slow speed of operation due to many levels of logic required for computation of correlation[2][3]. This paper suggests the new various architectures, which are systolic array architecture, simple pipeline architecture and block systolic array architecture[4][5]. The acquisition performance of the proposed architectures is analyzed and compared with the existing architecture. The comparison results show that the systolic array architecture and the block systolic array architecture reduce the timing delay up to 73% and 31%, respectively. And the results show that the simple pipeline architecture reduces the timing delay up to 53%..

• ETRI Journal
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• 제10권3호
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• pp.125-140
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• 1988

Computational geometry has wide applications in pattern recognition, image processing, VLSI design, and computer graphics. Voronoi diagrams in computational geometry possess many important properites which are related to other geometric structures of a set of point. In this pater the design of systolic algorithms for the static and the dynamic Voronoi diagrams is considered. The major motivation for developing the systolic architecture is for VLSI implementation. A new systematic transform technique for designing systolic arrays, in particular, for the problem in computational geometry has been proposed. Following this procedure, a type T systolic array architecture and associated systolic algorithms have been designed for constructing Voronoi diagrams. The functions of the cells in the array are also specified. The resulting systolic array achieves the maximal throughput with O(n) computational complexity.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• 전자공학회논문지S
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• 제34S권10호
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• pp.132-140
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• 1997

This paper proposes systolic array architectures for compuataion of the 1-D and 2-D discrete wavelet transform (DWT). The proposed systolic array for compuataion of the 1-D DWT consists of L processing element (PE) arrays, where the PE array denotes the systolic array for computation of the one level DWT. The proposed PE array computes only the product terms that are required for further computation and the outputs of low and high frequency filters are computed in alternate clock cycles. Therefore, the proposed architecuter can compute the low and high frequency outputs using a single architecture. The proposed systolic array for computation of the 2-D DWT consists of two systolic array architectures for comutation of the 1-D DWT and memory unit. The required time and hardware cost of the proposed systolic arrays are comparable to those of the conventional architectures. However, the conventional architectures need extra processing units whereas the proposed architectures fo not. The proposed architectures can be applied to subband decomposition by simply changing the filter coefficients.

• 대한전자공학회논문지SD
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• 제42권12호
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• pp.45-52
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• 2005

시스톨릭 어레이는 동일한 기능을 가지는 계산처리들을 동일한 형태로 연결하여, 다수의 자료에 반복적인 계산을 하도록 만들어진 병렬처리기로써 개념적으로 산술 파이프라인과 밀접한 관계를 갖는다. 시스톨릭 어레이 셀 내의 연산에 대한 고성능처리는 시스톨릭 어레이의 중요한 특징이다. 본 논문에서는 시스톨릭 어레이 셀 내의 동시성 처리를 높이기 위해 셀 내의 연산 중에서는 큰 지연 시간을 가지는 셀 내의 연산자를 다시 규칙성을 가지는 시스톨릭 어레이로 구성하는 비트 수준 슈퍼 시스톨릭 어레이 구조를 제안하고, 그 예로 비트 수준 슈퍼 시스톨릭 FIR 필터에 대하여 기술한다. 먼저 정규순환방정식으로 표현된 알고리즘으로부터 워드 수준 시스톨릭 어레이를 유도한 후 유도된 워드 수준 시스톨릭 어레이를 슈퍼 시스톨릭 어레이로 변환한다. 위의 과정으로 유도된 비트 수준 슈퍼 시스톨릭 어레이를 RT 수준에서 VHDL로 모델링 하여 동작을 검증하였으며, Hynix에서 제공되는 $0.35{\mu}m$셀 라이브러리를 사용하여 합성하였다. 본 논문에서 제안하는 비트 수준 슈퍼 시스톨릭 어레이는 워드 수준 시스톨릭 어레이 디자인에 비해 면적은 물론 성능측면에서 이점을 가진다.

• 전자공학회논문지SC
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• 제39권5호
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• pp.34-42
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• 2002

본 논문에서는 움직임 추정을 위한 블럭정합 알고리즘의 고속 처리를 위한 VLSI 어레이의 구조를 설계하였다. 완전탐색 블럭정합 알고리즘의 데이터 의존관계로부터 일차원 시스톨릭 어레이를 유도했다. 제안된 일차원 시스톨릭 어레이에 입력된 데이터와 제어신호는 인접한 처리요소를 통해서 전달되어 재사용된다. 따라서 제안된 시스톨릭 어레이는 시간 및 공간적 지역성을 만족한다. 데이터와 제어신호의 입출력 핀은 일차원 어레이의 시작과 끝의 처리요소에만 존재한다. 이 구조는 입력포트의 수가 적으며, 모듈러 확장성을 갖는다. 기준블럭과 최대탐색거리가 확장된 경우에 제안된 어레이를 연결하여 움직임 추정기를 구성할 수 있다.

• 인터넷정보학회논문지
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• 제7권1호
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• pp.49-57
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• 2006

본 논문에서는 128-bit 블록암호인 SEED 알고리즘을 하드웨어로 구현하는데 있어서 면적을 줄이고 연산속도를 증가시키는 회로구조에 대하여 논하였고 설계결과를 기술하였다. 연산속도를 증가시키기 위해 pipelined systolic array 구조를 사용하였으며, 입출력회로에 어떤 버퍼도 사용하지 않는 간단한 구조이다. 이 회로는 10 MHz 클럭을 사용하여 최대 320 Mbps의 암호화속도를 달성할 수 있다. 회로설계는 VHDL 코딩방식으로 수행하였으며, 50,000 gates 급의 FPGA에 구현하였다.

• 전자공학회논문지B
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• 제33B권2호
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• pp.103-110
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• 1996

In this paper, we propose a unified systolic array for the computation of the 2D discrete cosine transform/discrete sine transform/discrete hartley transform (DCT/DST/DHT). The unified systeolic array for the 2D DCT/DST/DHT is a generalization of the unified systolic array for the 1D DCT/DST/DHT. In order to calculate the 2D transform, we compute 1D transforms along the row, transpose them, and obtain 1D transforms along the column. When we compare the proposed systolic array with the conventional method, our architecture exhibits a lot of advantages in terms of latency, throughput, and the number of PE's. The simulation results using very high speed integrated circuit hardware description language (VHDL), international standard language for hardware description, show the functional validity of the proposed architecture.

• 정보학연구
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• 제10권3호
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.