• Title/Summary/Keyword: system-on-a-chip

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Single-Chip Microprocessor Control for Switched Reluctance Motor Drive

  • Hao Chen;Ahn, Jin-Woo
    • KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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    • v.2B no.4
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    • pp.207-213
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    • 2002
  • The paper introduces a switched reluctance motor drive system based on an 80C31 and an Intel 80C 196KB single-chip microprocessor control. Advance schemes are used in turn-on and turn-off angles with the power converter's main switches during traction and regenerative braking. The principles of traction speed control and braking torque control are given. The hardware and software patterns in the 80c31 and the Intel 80C196KB single-chip microprocessor control system are also presented.

The Subjective Evaluation on White Light Property and Color Appearance of Single Chip LED and RGB Multi Chip LED (단일칩 LED와 RGB 멀티칩 LED의 백색광 특성 및 색 보임에 대한 주관평가 연구)

  • Sim, Yun-Ju;Kim, In-Tae;Choi, An-Seop
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.29 no.1
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    • pp.1-8
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    • 2015
  • To produce the white light, there are a single chip method using the blue light and phosphor coating, a multi chip method by mixing R, G, B light.. Multi chip method is proper for the smart lighting system by controling color and color temperature. And color rendering of single chip LED is good by even spectral distribution. To apply application technic like smart light system, this paper analyzed the properties of single chip LED and RGB multi chip LED, and implemented the 2 part subject evaluation for single chip LED and RGB multi chip LED. The first part is comparison of properties for single chip LED and RGB multi chip and second part is color appearance evaluation of 8 colors in each lighting environment.

A Bus Data Compression Method on a Phase-Based On-Chip Bus

  • Lee, Jae-Sung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.117-126
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    • 2012
  • This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

SOC를 위한 효율적인 IP 재활용 방법론

  • 배종훈
    • The Magazine of the IEIE
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    • v.29 no.1
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    • pp.66-72
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    • 2002
  • VLSI 기술의 발전은 보다 많은 양의 로직을 단일 칩에 집적 가능하게 했고, 이는 System-on-a-chip 시대의 도래를 가능하게 했다. System-on-a-chip을 가능하게 하기 위해서는 많은 종류의 IP (Intellectual Property)가 필요하고, 공정 변환을 쉽게 하기 위해서는 합성이 가능한 RTL 설계가 절실히 요구된다. 본 논문은 이러한 요구에 부응하기 위해서 hard macro 형태의 기존의 IP로 부터 합성 가능한 IP를 자동 생성해 주는 ART(Automatic RTL Translation)로 명명된 기법에 관한 것이다. 제안된 ART 기법을 이용하여 80C52 호환의 8-bit MCU(Micro-controller Unit)의 합성 가능한 RTL model을 자동 생성하였고, 개발된 Soft IP를 이용하여 TCP/IP 전용 MCU를 표함해서 다양한 제품들을 개발하였다.

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Quantitative and Rapid Analysis of Transglutaminase Activity Using Protein Arrays in Mammalian Cells

  • Kwon, Mi-Hye;Jung, Jae-Wan;Jung, Se-Hui;Park, Jin-Young;Kim, Young-Myeong;Ha, Kwon-Soo
    • Molecules and Cells
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    • v.27 no.3
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    • pp.337-343
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    • 2009
  • We developed a novel on-chip activity assay using protein arrays for quantitative and rapid analysis of transglutaminase activity in mammalian cells. Transglutaminases are a family of $Ca^{2+}$-dependent enzymes involved in cell regulation as well as human diseases such as neurodegenerative disorders, inflammatory diseases and tumor progression. We fabricated the protein arrays by immobilizing N,N'-dimethylcasein (a substrate) on the amine surface of the arrays. We initiated transamidating reaction on the protein arrays and determined the transglutaminase activity by analyzing the fluorescence intensity of biotinylated casein. The on-chip transglutaminase activity assay was proved to be much more sensitive than the $[^3H]putrescine$-incorporation assay. We successfully applied the on-chip assay to a rapid and quantitative analysis of the transglutaminase activity in all-trans retinoic acid-treated NIH 3T3 and SH-SY5Y cells. In addition, the on-chip transglutaminase activity assay was sufficiently sensitive to determine the transglutaminase activity in eleven mammalian cell lines. Thus, this novel on-chip transglutaminase activity assay was confirmed to be a sensitive and high-throughput approach to investigating the roles of transglutaminase in cellular signaling, and, moreover, it is likely to have a strong potential for monitoring human diseases.

Injection Mold Technology of Protein Chip for Point-of-Care (현장진단용 단백질 칩 사출금형기술)

  • Lee, Sung-Hee;Ko, Young-Bae;Lee, Jong-Won;Jung, Hae-Chul;Park, Jae-Hyun;Lee, Ok-Sung
    • Design & Manufacturing
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    • v.6 no.2
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    • pp.74-78
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    • 2012
  • A multi-cavity injection mold system of protein chip for point-of-care with cavity temperature and pressure sensors was proposed in this work. In advance of manufacturing for the multi-cavity injection mold system, a single cavity injection mold system to mold protein chip was considered. Injection molding analysis for the presented system was performed to optimize the process of the molding and suggest guides to design. On the basis of the results for the single cavity system, a multi-cavity injection mold system for protein chip was analyzed, designed and manufactured with cavity temperature and pressure sensors. Results of balanced filling for protein chip models were obtained from the presented mold system.

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System-on-chip single event effect hardening design and validation using proton irradiation

  • Weitao Yang;Yang Li;Gang Guo;Chaohui He;Longsheng Wu
    • Nuclear Engineering and Technology
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    • v.55 no.3
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    • pp.1015-1020
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    • 2023
  • A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.

Prediction of Chip Formation Mechanism Using Acoustic Emission (음향방출을 이용한 칩 발생 기구의 예측)

  • 맹민재
    • Journal of the Korean Society of Safety
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    • v.16 no.2
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    • pp.22-26
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    • 2001
  • The machining process on be considered as a planned interaction of the workpiece, the tool and the machine tool. In an unmanned situation, the results of this interaction are to be continuously monitored so that any changes in the machining environment on be sensed to corrective actions. In order to design the process monitoring system for unmanned manufacturing, the identification of chip formation is proposed. The system proposes the method of using acoustic emission(AE) signal analysis to identify the chip formation during cutting.

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Microarchitecture Simulator for On-Chip Multiprocessor Microprocessor (다중처리형 마이크로프로세서 미세구조 시뮬레이터)

  • Park, Kyoung;Hahn, Woo-Jong
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.408-411
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    • 1999
  • Microarchitecture simulator is an important tool to verify and optimize the microarchitecture of a new microprocessor. Moreover. it can be use as a performance simulator to estimate the target microprocessor′s performance. And system software designers can use it as a software developing environment. This paper describes a "microarchitecture simulator for on-chip Multiprocessor microprocessor". It is a program-driven and cycle-based simulator that can execute simultaneous mutithreading benchmarks. We verified the microarchitecture of a new on-chip multiprocessor microprocessor with it and did performance simulations to estimate the performance of the on-chip multiprocessor microprocessor.

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Sensorless Speed Control of Induction Motor Based on System-On-A-Chip Design (원칩 설계에 의한 유도전동기의 센서리스 속도제어)

  • Lee, H.J.;Kim, S.J.;Lee, J.H.;Kwon, Y.A.
    • Proceedings of the KIEE Conference
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    • 2000.07b
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    • pp.1102-1104
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    • 2000
  • Recently effective system-on-a-chip design methodology is developed, and ASIC chip design is much studied for motor control. This paper investigates the design and implementation of ASIC chip for sensorless speed control of induction motor using VHDL which is a standarded hardware description language. The sensorless control strategy is to design an adaptive state observer for flux estimation and to estimate the rotor speed from the estimated rotor flux and stator current. The presented system is implemented using a simple electronic circuit based on FPGA.

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