• Journal of Internet Computing and Services
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• v.25 no.1
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• pp.29-37
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• 2024

In this paper, we propose an efficient image processing system to detect and track the movement of specific objects such as patients. The proposed system extracts the outline area of an object from a binarized difference image by applying a thinning algorithm that enables more precise detection compared to previous algorithms and is advantageous for mixed-mode design. The binarization and thinning steps, which require a lot of computation, are designed based on RTL (Register Transfer Level) and replaced with optimized hardware blocks through logic circuit synthesis. The designed binarization and thinning block was synthesized into a logic circuit using the standard 180n CMOS library and its operation was verified through simulation. To compare software-based performance, performance analysis of binary and thinning operations was also performed by applying sample images with 640 × 360 resolution in a 32-bit FPGA embedded system environment. As a result of verification, it was confirmed that the mixed-mode design can improve the processing speed by 93.8% in the binary and thinning stages compared to the previous software-only processing speed. The proposed mixed-mode system for object recognition is expected to be able to efficiently monitor patient movements even in an edge computing environment where artificial intelligence networks are not applied.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1296-1302
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using $0.18{\mu}m$ CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.

• Journal of Satellite, Information and Communications
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• v.11 no.4
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• pp.1-9
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• 2016

This paper was studied in two ways with respect to the information received from the video signal separation technique of PPI Scop radar device. The proposed technique consists in generating an image signal through the video signal separation and synthesis, symbol generation, the residual image signal generation process. This technology can greatly improve the operating convenience with improved ease of discrimination, screen readability for the operator in analyzing radar information. The first proposed method was constructed for high-speed FPGA-based information processing systems for high speed operation stability of the system. The second proposed method was implemented intelligent algorithms and a software algorithm function curve associated resources.This was required to meet the constraints on the radar information, analysis system. Existing radar systems have not the frame data analysis unit image. However, this study was designed to image data stored in the frame-by-frame analysis of radar images with express information MPEG4 video. Key research content is to highlight the key observations expresses the target, the object-specific monitoring information to the positive image processing algorithm and the function curve delays. For high-definition video, high-speed to implement data analysis and expressing a variety of information was applied to the ARM Processor Support in Pro ASIC3.

• International Journal of Aeronautical and Space Sciences
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• v.8 no.1
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• pp.10-20
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• 2007

For spacecraft attitude control, reaction wheel (RW) steering laws with more than three wheels for three-axis attitude control can be derived by using a control allocation (CA) approach.1-2 The CA technique deals with a problem of distributing a given control demand to available sets of actuators.3-4 There are many references for CA with applications to aerospace systems. For spacecraft, the control torque command for three body-fixed reference frames can be constructed by a combination of multiple wheels, usually four-wheel pyramid sets. Multi-wheel configurations can be exploited to satisfy a body-axis control torque requirement while satisfying objectives such as minimum control energy.1-2 In general, the reaction wheel steering laws determine required torque command for each wheel in the form of matrix pseudo-inverse. In general, the attitude control command is generated in the form of a feedback control. The spacecraft body angular rate measured by gyros is used to estimate angular displacement also.⁵ Combination of the body angular rate and attitude parameters such as quaternion and MRPs(Modified Rodrigues Parameters) is typically used in synthesizing the control command which should be produced by RWs.¹ The attitude sensor signals are usually corrupted by noise; gyros tend to contain errors such as drift and random noise. The attitude determination system can estimate such errors, and provide best true signals for feedback control.⁶ Even if the attitude determination system, for instance, sophisticated algorithm such as the EKF(Extended Kalman Filter) algorithm⁶, can eliminate the errors efficiently, it is quite probable that the control command still contains noise sources. The noise and/or other high frequency components in the control command would cause the wheel speed to change in an undesirable manner. The closed-loop system, governed by the feedback control law, is also directly affected by the noise due to imperfect sensor characteristics. The noise components in the sensor signal should be mitigated so that the control command is isolated from the noise effect. This can be done by adding a filter to the sensor output or preventing rapid change in the control command. Dynamic control allocation(DCA), recently studied by Härkegård, is to distribute the control command in the sense of dynamics⁴: the allocation is made over a certain time interval, not a fixed time instant. The dynamic behavior of the control command is taken into account in the course of distributing the control command. Not only the control command requirement, but also variation of the control command over a sampling interval is included in the performance criterion to be optimized. The result is a control command in the form of a finite difference equation over the given time interval.⁴ It results in a filter dynamics by taking the previous control command into account for the synthesis of current control command. Stability of the proposed dynamic control allocation (CA) approach was proved to ensure the control command is bounded at the steady-state. In this study, we extended the results presented in Ref. 4 by adding a two-step dynamic CA term in deriving the control allocation law. Also, the strict equality constraint, between the virtual and actual control inputs, is relaxed in order to construct control command with a smooth profile. The proposed DCA technique is applied to a spacecraft attitude control problem. The sensor noise and/or irregular signals, which are existent in most of spacecraft attitude sensors, can be handled effectively by the proposed approach.

• Clean Technology
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• v.24 no.3
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• pp.239-248
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• 2018

In this study, pervaporation experiments of water, ethanol and IPA (Isopropyl alcohol) single components and water/ethanol, water/IPA mixtures were carried out using zeolite 4A membranes developed by Fine Tech Co. Ltd. Those membranes were fabricated by hydrothermal synthesis (growth in hydrothermal condition) after uniformly dispersing the zeolite seeds on the tubular alumina supports. They have a pore size of about $4{\AA}$ by ion exchange of $Na^+$ to the LTA structure with Si/Al ratio of 1.0, and shows strong hydrophilic property. Physical characteristics of prepared membranes were evaluated by using SEM (surface morphology), porosimetry (macro- or meso- pore analysis), BET (micropore analysis), and load tester (compressive strength). Pervaporation experiments with various temperature and concentration conditions confirmed that the zeolite 4A membrane can selectively separate water from ethanol and IPA. Water/ethanol separation factor was over 3,000 and water/IPA separation factor was over 1,500 (50 : 50 wt%, initial feed concentration). Pervaporation behaviors of single components and binary mixtures were predicted using ACM (activity coefficient model), GMS (generalized Maxwell Stefan) model and DGM (Dusty Gas Model). The adsorption and diffusion coefficients of the zeolite top layer were obtained by parameter estimation using GA (Genetic Algorithm, stochastic optimization method). All the calculations were carried out using MATLAB 2018a version.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.4
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• pp.372-381
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• 2001

In this paper SEED, the Korea Standard 128-bit block cipher algorithm is implemented with VHDL and mapped into one FPGA. SEED consists of round key generation block, F function block, G function block, round processing block, control block and I/O block. The designed SEED is realized in an FPGA but we design it technology-independently so that ASIC or core-based implementation is possible. SEED requires many hardware resources which may be impossible to realize in one FPGA. So it is necessary to minimize hardware resources. In this paper only one G function is implemented and is used for both the F function block and the round key block. That is, by using one G function sequentially, we can realize all the SEED components in one FPGA. The used cell rate after synthesis is 80% in Altem FLEXI0KlOO. The resulted design has 28Mhz clock speed and 14.9Mbps performance. The SEED hardware is technology-independent and no other external component is needed. Thus, it can be applied to other SEED implementations and cipher systems which use SEED.

• Journal of Broadcast Engineering
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• v.19 no.5
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• pp.713-725
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• 2014

Multi-view and 3D video technologies for a next generation video service are widely studied. These technologies can make users feel realistic experience as supporting various views. Because acquisition and transmission of a large number of views require a high cost, main challenges for multi-view and 3D video include view synthesis, video coding, and depth coding. Recently, JCT-3V (joint collaborative team on 3D video coding extension development) has being developed a new standard for multi-view and 3D video. In this paper, major tools adopted in this standard are introduced and evaluated in terms of coding efficiency and complexity. This performance analysis would be helpful for the development of a fast 3D video encoder as well as a new 3D video coding algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.905-912
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• 2007

This paper proposes an efficient estimation and compensation scheme of IQ imbalance for OFDM-based WLAN systems in the presence of symbol timing error. Since the conventional scheme assumes perfect time synchronization, the criterion of the scheme used to derive the estimation of IQ imbalance is inadequate in the presence of the symbol timing error and the system performance is seriously degraded. New criterion and compensation scheme considering the effect of symbol timing error are proposed. With the proposed scheme, the IQ imbalance can be almost perfectly eliminated in the presence of symbol timing error. The bit error rate performance of the proposed scheme is evaluated by the simulation. In case of 54 Mbps transmission mode in IEEE 802.11a system, the proposed scheme achieves a SNR gain of 4.3dB at $BER=2{\cdot}10^{-3}$. The proposed compensation algorithm of IQ imbalance is implemented using Verilog HDL and verified. The proposed IQ imbalance compensator is composed of 74K logic gates and 6K bits memory from the synthesis result using 0.18um CMOS technology.

• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.31-40
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• 2012

In this paper, we propose a method of synthesizing faces of a user and an animation character using a 3D face model. The suggested method first receives two orthogonal 2D face images and extracts major features of the face through the template snake. It then generates a user-customized 3D face model by adjusting a generalized face model using the extracted facial features and by mapping texture maps obtained from two input images to the 3D face model. Finally, it generates a user-customized animation character by synthesizing the generated 3D model to an animation character reflecting the position, size, facial expressions, and rotational information of the character. Experimental results show some results to verify the performance of the suggested algorithm. We expect that our method will be useful to various applications such as games and animation movies.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.12
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• pp.513-519
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• 2002

This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing(OFDM) systems. The Proposed architecture uses a single-memory architecture and uses a radix-4 algorithm for high speed. The proposed memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. Therefore, the memory size can be reduced. The SQNR of about 80dB is achieved with 20-bit input and 20-bit twiddle factors. The architecture has been modeled by VHDL and logic synthesis has been performed using the SamsungTM 0.5㎛ SOG cell library (KG80). The implemented FFT processor consists of 98,326 gates excluding memory. It has smaller hardware than existing pipeline FFT processors for more than 1024-point FFTs. The processor can operate at 42MHz and calculate a 256-point complex FFT in 6us. It satisfies tile required processing speed of 8.4㎲ in the HomePlug standard.