• Journal of the Institute of Convergence Signal Processing
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• v.6 no.1
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• pp.39-44
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• 2005

Scheduling for digital system synthesis is assigning each operation in a control/data flow graph(CDFG) to a specific control step without violating precedence relation. It is one of the most important tasks due to its direct influence on the performance of the hardware synthesized. In this paper, we propose a resource-constrained scheduling algorithm. Our algorithm first analyzes the given CDFG to determine the number of functional units of each type, then assigns each operation to a control step while satisfying the constraints. It also tries to improve the solution iteratively by adjusting the number of functional units using the results collected from the previous scheduling. Experiments were performed to test the performance of the proposed algorithm, and results are presented

• Journal of Information Processing Systems
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• v.13 no.5
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• pp.1183-1202
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• 2017

Image restoration has been carried out by texture synthesis mostly for large regions and inpainting algorithms for small cracks in images. In this paper, we propose a new approach that allows for the simultaneous fill-in of different structures and textures by processing in a wavelet domain. A combination of structure inpainting and patch-based texture synthesis is carried out, which is known as patch-based inpainting, for filling and updating the target region. The wavelet transform is used for its very good multiresolution capabilities. The proposed algorithm uses the wavelet domain subbands to resolve the structure and texture components in smooth approximation and high frequency structural details. The subbands are processed separately by the prioritized patch-based inpainting with isophote energy driven texture synthesis at the core. The algorithm automatically estimates the wavelet coefficients of the target regions of various subbands using optimized patches from the surrounding DWT coefficients. The suggested performance improvement drastically improves execution speed over the existing algorithm. The proposed patch optimization strategy improves the quality of the fill. The fill-in is done with higher priority to structures and isophotes arriving at target boundaries. The effectiveness of the algorithm is demonstrated with natural and textured images with varying textural complexions.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2017.06a
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• pp.83-84
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• 2017

We propose a novel high dynamic range (HDR) video synthesis algorithm from alternatively exposed low dynamic range (LDR) videos. We first estimate correspondences between input fames using an illumination invariant descriptor. Then, we synthesize an HDR frame with the weights computed to maximize detail preservation in the output HDR frame. Experimental results demonstrate that the proposed algorithm provides high-quality HDR videos without noticeable artifacts.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.1
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• pp.74-84
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• 1991

This paper presents an algorithm for technology-dependent logic optimization and technology mapping, and describes a performance-driven logic synthesis system, SILOS, implemented based on the proposed algorithm. The system analyzes circuits and resynthesizes the critical sections such that generated circuit operates opertes within time constraints, using only gate types supported by library for direct implementation. Experimental results show that the system can be a viable tool in synthesizing high-performance logic circuits.

• International Journal of Computer Science & Network Security
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• v.21 no.3
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• pp.304-310
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• 2021

The paper presents problems of optimization of the synthesis of embedded systems, in particular Pareto optimization. The model of such a system for its design for high-level of abstract is based on the classic approach known from the theory of task scheduling, but it is significantly extended, among others, by the characteristics of tasks and resources as well as additional criteria of optimal system in scope structure and operation. The metaheuristic algorithm operating according to this model introduces a new approach to system synthesis, in which parallelism of task scheduling and resources partition is applied. An algorithm based on a genetic approach with simulated annealing and Boltzmann tournaments, avoids local minima and generates optimized solutions. Such a synthesis is based on the implementation of task scheduling, resources identification and partition, allocation of tasks and resources and ultimately on the optimization of the designed system in accordance with the optimization criteria regarding cost of implementation, execution speed of processes and energy consumption by the system during operation. This paper presents examples and results for multi-criteria optimization, based on calculations for specifying non-dominated solutions and indicating a subset of Pareto solutions in the space of all solutions.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.7
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• pp.1025-1035
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• 1995

In this paper, we realize a real time digital FM synthesizer based on genetic algorithm using a general purpose digital signal processor. Especially, we synthesize diverse music sounds nicely using a synthesis model consisting of a single modulator and multiple carriers. Also we present genetic algorithm-based technique which determines optimal parameters for reconstruction through FM synthesis of a sound after analyzing the spectrum of PCM data as a standard music sound using FFT. Using the suggested parameter extractiuon algorithm, we extract parameters of several instruments and then synthesize digital FM sounds. To verify the validity of the parameter extraction algorithm as well as realization of a real time digital music synthesizer, the evaluation is first done by listening the sound directly as subjective test. Secondly, to evaluate the synthesized sound objectively with an engineering sense, we compare the synthesized sound with an original one in a time domain and a frequency domain.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.7
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• pp.117-124
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• 1994

In this pape, we propose a graph-theoretic approach for solving the allocation problem for the synthesis of datapaths based on multiport memories. An efficient algorithm is devised by using the weighted bipartite matching algorithm to assign variables to each port of memory modules. The proposed algorithm assigns program variables into a minimum number of multiport memory modules such that usage of memory elements and interconnection cost can be kept minimal. Experimental results show that the proposed algorithm generates the datapaths with fewer registers in memory modules and less interconnection cost for several benchmarks available from the literatures.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.10
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• pp.126-131
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• 1999

Up until now, it is said that no satisfactory computer solutions have been found for synthesizing four-bar linkage based on the prescribed coupler link curve. In our study, an algorithm has been developed to improve the design synthesis of four-bar linkage automatically generating prescribed path by using B-spline interpolation. The suggested algorithm generates the desired coupler curve by using B-spline interpolation, and hence the generated curve approximates as closely as to the desired curve representing coupler link trajectory. Also, when comparing each generated polygon with the control polygon, rapid comparison by applying convex hull concept. finally, optimization process using ADS is incorporated into the algorithm based on the 5 precision point method to reduce the total optimization process time. As for examples, three different four-bar linkages were tested and the results showed the effectiveness of the algorithm.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.69-72
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level syntehsis consist of compiling, partitioning, scheduling This paper we study the partitioning process, and analysis the min-cut algorithm and simulated annealing algorithm.

• The Journal of the Acoustical Society of Korea
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• v.28 no.2
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• pp.119-126
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• 2009

This paper describes the non-stringed guitar composed of laser strings, frets, sound synthesis algorithm and a processor. The laser strings that can depict stroke and playing arpeggios comprise laser modules and photo diodes. Frets are implemented by voltage divider. The guitar body does not need to implement physically because commuted waveguide synthesis is used. The proposed frets enable; players to represent all of chords by the chord glove as well as guitar solo. Sliding, hammering-on and pulling-off sounds are synthesized by using parameters from the voltage divider. Because the pitch shifting corresponds to the time-varying propagation speed in the digital waveguide model, the proposed model can synthesize vibrato as well. After transformation of signals from the laser strings and frets into parameters for synthesis algorithm, the digital signal processor, TMS320F2812, performs the real-time synthesis algorithm and communicates with the DAC. The demonstration movieclip available via the Internet shows one to play a song, 'Arirang', synthesized by proposed algorithm and interfaces in real-time. Consequently, we can conclude that the proposed synthesis algorithm is efficient in guitar solo and there is no problem to play the non-stringed guitar in real-time.