• Proceedings of the IEEK Conference
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• summer
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• pp.70-73
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• 2004

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array (FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.381-384
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• 2002

In speech signal processing, it Is very important to detect the pitch exactly in speech recognition, synthesis and analysis. but, it is very difficult to pitch detection from speech signal because of formant and transition amplitude affect. therefore, in this paper, we proposed a pitch detection using the spectrum flattening techniques. Spectrum flattening is to eliminate the formant and transition amplitude affect. In time domain, positive center clipping is process in order to emphasize pitch period with a glottal component of removed vocal tract characteristic. And rough formant envelope is computed through peak-fitting spectrum of original speech signal in frequency domain. As a results, well get the flattened harmonics waveform with the algebra difference between spectrum of original speech signal and smoothed formant envelope. After all, we obtain residual signal which is removed vocal tract element The performance was compared with LPC and Cepstrum, ACF 0wing to this algorithm, we have obtained the pitch information improved the accuracy of pitch detection and gross error rate is reduced in voice speech region and in transition region of changing the phoneme.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.401-404
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• 2002

In general, speech coding methods are classified into the following three categories: the waveform coding, the source coding and the hybrid coding. In this paper, First, the reference waveform is detected after searching the pitch period by NAMDF similarity and similarity between the reference waveform and the waveform each pitch period. It made a decision whether the waveform is compressed with the threshold of similarity. If the waveform is compressed only magnitude and pitch information is transmitted into the input of G.723.1 vocoder. Performing through the G.723.1 vocoder, the waveform is restored with the magnitude and pitch information by PSOLA synthesis method. The result of simulation with proposed algorithm has a 31% reduction of bit rate than the standard 5.3kbps G.723.1 ACELP vocoder.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.7
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• pp.147-153
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• 1996

For shape invariant recognitin of korean characters iwth noise, an optical wavelet SDF filter is proposed To preserve the features of a reference image and inimize effects of a random noise in the inpt image wavelet transformed images with different dialation parameters are used. And to adapt to divese variations in the combinatorial form, eCP-SDF filter synthesis algorithm is used. The proposed optical wavelet SDF filter is the type of the matched filter so that it can use the structure of 4f optical correlation system. The computer simulation results show that the proposed filter is useful in the noisy input.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.261-273
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• 2016

Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) full-parallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.

• KIEE International Transaction on Systems and Control
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• v.2D no.2
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• pp.108-114
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• 2002

This paper describes the design of a robust adaptive controller for a nonlinear dynamical system with unknown nonlinearities. These unknown nonlinearities are approximated by multilayered neural networks (MNNs) whose parameters are adjusted on-line, according to some adaptive laws far controlling the output of the nonlinear system, to track a given trajectory. The main contribution of this paper is a method for considering input constraint with a rigorous stability proof. The Lyapunov synthesis approach is used to develop a state-feedback adaptive control algorithm based on the adaptive MNN model. An overall control system guarantees that the tracking error converges at about zero and that all signals involved are uniformly bounded even in the presence of input saturation. Theoretical results are illustrated through a simulation example.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2280-2282
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• 2000

This paper presents a simple and new digital redesign algorithm for fussy-model-based controllers. In the first stage, a continuous-time TS fuzzy model is constructed for a given continuous-time nonlinear system and a corresponding continuous-time fuzzy-model-based controller is established based on the existing controller synthesis algorithms. In the second stage, the continuous-time fuzzy-model-based controller is converted to equivalent discrete-time fuzzy-model-based controller, aiming at maintaining the property of the analogue controlled system, which are called intelligent digital redesign. Finally, the proposed method is applied to the digital control of inverted pendulum system to shows the effectiveness and the feasibility of the method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.11a
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• pp.56-59
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• 2015

본 논문에서는 스테레오 오디오 신호를 이용하여 음원을 분리하는 ADRess 알고리즘을 기반으로, 추정된 음원 방위각에 대한 신호 강도비를 이용하여 분리음원을 생성하는 새로운 분리음원 합성 기법을 제안한다. 입력된 스테레오 채널 신호 간 강도 차(IID) 특성을 이용하여 신호 분석 프레임별로 개선된 신호 강도비 함수에 따른 frequency-azimuth 평면을 구성하고, 이를 통해 추정된 방위각에 상응하는 신호 강도비로 표현되는 확률밀도함수를 좌/우 신호 중 하나의 주 입력 신호에 취함으로써 분리음원을 합성한다. 제안된 기법의 성능을 검증하기 위하여 SASSEC 에서 제공하는 테스트 음원 및 객관적 평가 지표를 이용하여 측정한 결과, 기존 ADRess 알고리즘에서 제시된 방법에 비해 개선된 품질의 분리음원을 합성하는 것으로 평가되었다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.1
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• pp.43-49
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• 1992

As a result of recent progress in speech synthesis techniques, the those new services using new techniques are going to introduce into the telephone communication system. In setting standards, voice quality is obviously an important criterion. It is very important to develope a quality evaluation method of synthesized speech for the diagnostic assessment of system algorithm, and fair comparison of assessment values. This paper has described several basic concepts and criterions for quality assessment (intelligibility) of synthesized speech by rule, and then a word selection method and the word list to be used in word intelligibility test were proposed. Finally, a test method for word intelligibility is described.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.