• Journal of Power Electronics
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• v.17 no.6
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• pp.1445-1453
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• 2017

In this study, a new zero-voltage transition (ZVT) buck converter with coupled inductor using a synchronous rectifier and a lossless clamp circuit is proposed. The regular buck converter with tapped inductor has extended duty cycle for high step-down applications. However, the leakage inductance of the coupled inductor produced considerable voltage spikes across the switch. A lossless clamp circuit is used in the proposed converter to overcome this problem. The freewheeling diode was replaced with a synchronous rectifier to reduce conduction losses in the proposed converter. ZVT conditions at turn-on and turn-off instants were provided for the main switch. The synchronous rectifier switch turned on under zero-voltage switching, and the auxiliary switch turn-on and turn-off were under zero-current condition. Experimental results of a 100 W-100 kHz prototype are provided to justify the validity of the theoretical analysis. Moreover, the conducted electromagnetic interference of the proposed converter is measured and compared with its hard-switching counterpart.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.54 no.8
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• pp.401-409
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• 2005

This paper describes a feasibility analysis result of STATCOM application for the Jeju-Haenam HVDC system. The Jeju-Haenam HVDC system is one of the typical HVDC system interconnected with the low short-circuit-ratio AC system, which is vulnerable to the commutation failure due to the AC voltage variation. STATCOM has been considered as an effective reactive-power compensator to increase short-circuit-ratio of the interconnected AC system. In this study, a simulation model of Jeju-Hacnam HVDC system with STATCOM was developed using PSCAD/EMTDC. The developed simulation model was utilized to analyze the dynamic performance analysis of Jeju-Haenam HVDC system with STATCOM. The analysis results show that STATCOM can improve the dynamic performance of Jeju-Haenam HVDC system, such as load-change recovery performance and fault recovery performance.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.237-239
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• 2005

In this paper PLC Power Circuit with Hot-Swap Function is proposed for stable power supplies. The power modules of the proposed devices are implemented by CRM flyback converter using new synchronous rectifier circuit for high efficiency. By a variable switching frequency controller, this converter is operated with a reduced turn-on switching loss. Also, the load current in these power modules are shared by auto master / slave method using Outer loop. The proposed devices are analyzed in detail and optimized for high performance. Experimental results for a 100W power module at the variable switching frequency of 30$^{\sim}$70kHz were obtained to show the performance of the proposed device.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.3
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• pp.88-95
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• 2008

In the paper, the permanent magnet synchronous generator of 1.5[MW] output power which is driven directly without gear system is designed by conventional magnetic equivalent circuit method and analyzed by finite element method. We analyzed the characteristics of generator like no load, rated load, short circuit condition and demagnetization of permanent magnet in order to verify the design results by magnetic circuit method. The last, the analysis results of two kinds of rotor types are compared with each other. Especially the THD(total harmonic distortion) of output voltage is examined for the comparison.

• Journal of Communications and Networks
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• v.7 no.1
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• pp.1-12
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• 2005

Ethernet is being deployed in metropolitan area networks (MANs) as a lower-cost alternative to SONET-based infrastructures. MANs are usually required to support common communication services, such as voice and frame relay, based on legacy synchronous TDM technology in addition to asynchronous packet data transport. This paper addresses the clock synchronization problem that arises when transporting synchronous services over an asynchronous packet infrastructure, such as Ethernet. A novel algorithm for clock synchronization is presented combining time-stamp methods used in the network time protocol (NTP) with signal processing techniques applied to measured packet interarrival times. The algorithm achieves the frequency accuracy, stability, low drift, holdover performance, and rapid convergence required for viable emulation of TDM circuit services over Ethernet.

• Journal of Power Electronics
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• v.10 no.1
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• pp.27-33
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• 2010

This paper presents a bidirectional DC-DC converter suitable for low-voltage super capacitor-based electric energy storage systems. The DC-DC converter presented here consists of a full-bridge circuit and a current-fed push-pull circuit with a high frequency (HF) transformer-link. In order to reduce the device-conduction losses due to the large current of the super capacitor as well as unnecessary ringing, synchronous rectification is employed in the super capacitor-charging mode. A wide range of voltage regulation between the battery and the super capacitor can be realized by employing a Phase-Shifting (PS) Pulse Width Modulation (PWM) scheme in the full-bridge circuit for the super capacitor charging mode as well as the overlapping PWM scheme of the gate signals to the active power devices in the push-pull circuit for the super capacitor discharging mode. Essential performance of the bidirectional DC-DC converter is demonstrated with simulation and experiment results, and the practical effectiveness of the DC-DC converter is discussed.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.343-345
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• 1996

In the case of synchronous machines, certain power system disturbances cause current to assume negative values when no static converter is present. But the converter prevents negative current from flowing, so that overvoltages occur. The overvoltages can be effectively limited as crowbar circuit using GTO. The crowbar circuit with current limiting resistor absorbs energy when overvoltage comes from power system repeatedly. The newly proposed circuit is verified through simulation and experiment

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.8
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• pp.514-521
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• 2000

This paper presents a direct thrust control scheme for permanent magnet linear synchronous motor(PMLSM) by using digital signal processor(DSP). And a simulation method for the direct thrust control of a permanent magnet linear synchronous motor using the equivalent circuit is presented. The detent force that was obtained by cubic spline method is considered in the simulation. Thrust correction coefficient is utilized to estimate actual thrust on the direct thrust control, which considers the longitudinal end effect due to the finite core length of the permanent magnet linear synchronous motor. The motor self inductance, the initial flux linkage by the permanent magnet is calculated in advance by the finite element analysis, and then the direct control simulation is carried out. As the results, thrust, current and speed are shwon.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.73-77
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• 1990

In this paper we describe the solid-state ac-circuit breaker which has the characteristic of both a half cycle circuit breaker and a current limiting circuit breaker. This circuit breaker has a current limiting resistor in order to surprises the fault current to a certain level and discharge the energe included in circuit inductor. We explain the effect of circuit parameter on transient phenomena of switch device by using EMTP and finally design the control circuit consisted synchronous closing circuit, over- current detecting circuit and sensing circuit of rate of rise of fault current.

• ETRI Journal
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• v.35 no.3
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• pp.480-490
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• 2013

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-${\mu}m$ CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 ${\mu}W$/MHz and is comparable to that of a synchronous counterpart.