• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.823-824
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• 2013

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.218-230
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• 1993

A power line modem(PLM) which transfers data safely through power lines in houses or small offices is considered. When a power line is used for communications, transmitted signals could be affected by the channel characteristics such as frequency-selective fading, interference, and time-varying attenuation. In order to overcome these impairments, a direct sequence(DS) technique which is well known as an effective instrument against a variety of interferences and hostile channel properties is employed. Using a DS technique, however, requires more circuits such as PN code generator circuits, code modification circuits, and complicated synchronization circuits, and it also results in substantial acquisition delay. In this paper, some of these circuits are implemented via software programmed in the system controller, and the complicated synchronization circuits are replaced by simple circuits utilizing a 60 Hz power signal for synchronization. The synchronization ciruits used in this paper virtually eliminate the substantial acquisition delay, and is also designed to free influence of 60 Hz zero crossing jitters which reside in a power signal. As a result, a PLM using a DS technique is realized in the form of wall-socket plug, and the PLM hardware would be very much simplified.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1152-1160
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• 2003

Start The current paper proposes an improved HD(High Definition) monitor that can support a signal input with various resolutions. Due to the inadequate performance of the built-in digital PLL(Phase-locked Loop) of an ADC(Analog to Digital Converter) and poor tolerance of ADC ICs, there are problems in the stable processing of synchronization signals with various input signals. Accordingly, the proposed synchronization signal optimization technique regenerates the horizontal synchronization signal in the vertical blanking interval based on the regularity of the synchronization signal, i.e. the timing of the falling edge signal remains constant, thereby solving the above problem and minimizing the interference of the system. As a result, the proposed system can stabilize various synchronization signals with different resolution modes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.11
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• pp.1022-1032
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• 2012

In OFDMA-based wireless mesh networks, synchronization of carrier frequencies among adjacent nodes is known to be difficult. In this paper, a distributed synchronization technique is proposed to solve the synchronization problem in OFDMA-based wireless mesh networks by using the bio-inspired algorithm. In the proposed approach, carrier frequencies of all nodes in a mesh network are converged into one frequency by locally synchronizing the frequencies of adjacent nodes. It may take a long time to be converged in some topologies since the convergence characteristic of carrier frequencies in a mesh network may vary depending on the size of the network and deployment of nodes. It is shown that fast frequency synchronization, not heavily depending on the topology, can be achieved through the proposed algorithm with an adjustable weight.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.65-76
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• 2004

In this paper, a novel preamble structure, including a synchronization preamble and a cell search preamble, is proposed for OFDM-based cellular systems. An efficient algorithm for downlink synchronization and cell searching using the preamble is also proposed. The synchronization process includes the initial symbol timing estimation using continuously, or at least, periodically transmitted downlink signal, frame synchronization, the fine symbol timing estimation, and the frequency offset estimation using the synchronization preamble, and the cell identification using the cell searching preamble. Performance of each synchronization and cell searching step is analyzed and the analytic results including the overall performance of the synchronization and cell searching are verified by computer simulation. It is shown that the proposed preamble with the corresponding synchronization and cell searching algorithm can provide very robust synchronization and cell searching capability even in bad cellular environments.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1939-1949
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• 2016

This paper presents an alternative frequency adaptive grid synchronization technique named HDN-FLL, which can accurately extract the fundamental positive- and negative-sequence components and interested harmonics in adverse three-phase grid voltage. The HDN-FLL is based on the harmonic decoupling network (HDN) consisting of multiple first order complex vector filters (FOCVF) with a frequency-locked loop (FLL), which makes the system frequency adaptive. The stability of the proposed FLL is strictly verified to be global asymptotically stable. In addition, the linearization and parameters tuning of the FLL is also discussed. The structure of the HDN has been widely used as a prefilter in grid synchronization techniques. However, the stability of the general HDN is seldom discussed. In this paper, the transfer function expression of the general HDN is deduced and its stability is verified by the root locus method. To show the advantages of the HDN-FLL, a simulation comparison with other gird synchronization methods is carried out. Experimental results verify the excellent performance of the proposed synchronization method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.2
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• pp.123-132
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• 2014

In this paper, an IEEE1588 based clock synchronization technique for CAN (Controller Area Network) is presented. Clock synchronization plays a key role to the success of a networked embedded system. Recently, the IEEE1588 algorithm making use of dedicated chipsets has been widely adopted for the synchronization of various industrial applications using Ethernet. However, there is no chipset available for CAN. This paper presents the implementation of IEEE1588 for CAN, which is implemented using only software and CAN packets without any dedicated chipset. The proposed approach is verified by the comparison between the estimated synchronization precision with a simple model and the measured precision with experimental setup.

• Journal of Sensor Science and Technology
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• v.16 no.1
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• pp.52-61
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• 2007

Networked embedded systems using the smart device and fieldbus technologies are now found in many industrial fields including process automation and automobiles. However the discrepancy between a node's view of current time and the rest of the system can cause many difficulties in the design and implementation of a networked system. To provide a networked system with a global reference time, the problem of clock synchronization has been intensively studied over the decades. However, many of the existing solutions, which are mainly developed for large scale distributed computer systems, cannot be directly applied to embedded systems. This paper presents a fault-tolerant clock synchronization technique that can be used for a low-cost embedded system using a CAN bus. The effectiveness of the proposed method is demonstrated with a set of microcontrollers and DC motor-based actuators.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.185-192
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• 2010

This paper presents a hardware-efficient auto-correlation scheme for the synchronization of MIMO-OFDM based wireless local area network (WLAN) systems, such as IEEE 802.11n. Carrier frequency offset (CFO) estimation for the frequency synchronization requires high complexity auto-correlation operations of many training symbols. In order to reduce the hardware complexity of the MIMO-OFDM synchronization, we propose an efficient correlation scheme based on time-multiplexing technique and the use of reduced samples while preserving the performance. Compared to a conventional architecture, the proposed architecture requires only 27% logic gates and 22% power consumption with acceptable BER performance loss.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.189-194
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• 2007

This paper derives and computes the detection probability of timing synchronization in an orthogonal frequency division multiplexing (OFDM) system encountered with a multipath Rayleigh fading channel and imperfect noise estimation. The timing synchronization scheme using a simple repeated constant amplitude zero auto-correlation (CAZAC) training symbol and correlation techniques is adopted. With this provision, we focus on the numerical analysis for OFDM timing synchronization scheme employing a preadvancement technique to reduce the inter-symbol interference (ISI). For measuring system performance, the detection performance derived in the considered system is presented in a multipath Rayleigh fading channel.