• Title/Summary/Keyword: symbol timing synchronization

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A Channel Estimation Technique Based on Pilot Tones for OFDM Systems with a Symbol Timing Offset (시간 동기 옵셋을 갖는 OFDM 시스템을 위한 파일럿 톤 기반의 채널 추정 기법)

  • Park, Chang-Hwan;Kim, Jae-Kwon;Lee, Hee-Soo;Cho, Yong-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.10A
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    • pp.992-1003
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    • 2007
  • In this paper, a channel estimation technique based on pilot tones, which does not degrade channel estimation performance even with the existence of symbol timing offset (STO) in OFDM systems, is proposed. The proposed technique performs channel estimation by interpolating channels with respect to amplitude and phase with a minimum computational complexity, differently from the conventional interpolation techniques. The proposed technique requires neither the estimation of fine STO in advance nor trigonometric operation for phase interpolation, signifying a significant reduction in computational complexity. Since the performance of the proposed technique does not depend on the STO present in OFDM systems. It can be directly applied to the following areas in OFDM-based communication system: elimination of fine STO estimation step in the synchronization procedure, elimination of STO estimation step in multiuser uplink, and channel estimation in multi-hop relay system. It is verified by computer simulation that the proposed technique can improve the performance of channel estimation significantly in the presence of STOs, compared with previous channel estimation techniques based on pilot tones.

Design of a Digital Burst MODEM for High-Speed ATM Satellite Communications Part I : Analysis of Synchronization Techniques (고속 ATM 위성통신을 위한 TDMA 버스트 모뎀 설계 1부 : 수신기 동기기술 분석)

  • Hwang, Sung-Hyun;Kim, Ki-Yun;Choi, Hyung-Jin
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.10
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    • pp.34-41
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    • 1998
  • In this paper, we evaluate synchronization techniques suitable for high-speed ATM satellite communications with a transmission rate of 155Mbit/s, and propose optimal algorithms that improve the tracking performance, where QPSK is selected for a modulation scheme, and the receiver is operated in burst mode. Based on these asumptions, we proposed modified algorithms and architectures for automatic frequency control(AFC), carrier recovery(CR), and symbol timing recovery(STR) for burst acquisition. Analysis is performed under AWGN environments with respect to the number of required symbol, steady-state stability, and hardware implementation for the proposed algorithms.

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A study on the design and implementation of uplink receiver for BWLL Base Station modem (광대역 무선가입자망 기지국용 모뎀의 상향링크 수신기 설계 및 구현에 관한 연구)

  • 남옥우;김재형
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2001.10a
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    • pp.307-310
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    • 2001
  • In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

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An Efficient Symbol Timing Synchronization Scheme for IEEE 802.11n MIMO-OFDM based WLAN Systems (IEEE 802.11n MIMO-OFDM 기반 무선 LAN 시스템을 위한 효율적인 심볼 동기 방법)

  • Cho, Mi-Suk;Jung, Yun-Ho;Kim, Jae-Seok
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.5
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    • pp.95-103
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    • 2009
  • An efficient symbol time synchronization scheme for IEEE 802.11n MIMO-OFDM based WLAN systems using cyclic shift diversity (CSD) preamble is proposed. CSD is used to prevent unintentional beamforming when the same preamble signal is transmitted through transmit antennas. However, it is difficult to find a proper starting-point of the OFDM symbol with the conventional algorithms because of time offset by multi-peaks which are result from cross-correlation of received CSD preamble with a known short training symbol. In addition, the performance of symbol time sync. is affected by AGC and packet detection position. In this paper, an optimal symbol time synch. algorithm which is composed of the boundary detection scheme between LTS and OFDM symbols, the verification scheme for enhancement of boundary detection accuracy, and the SNR-varying threshold estimation scheme is proposed. Simulation result show that the proposed algorithm has performance gains of 4.3dB in SNR compared to the conventional algorithms at the rate of 1% sync. failure probability for $2{\times}2$ MIMO-OFDM system and 18dB at 0.1% when maximum frequency offset exists. It also can be applied to $4{\times}4$ MIMO-OFDM system without any modification. Hence, it is very suitable for MIMO-OFDM WLAN systems using CSD preamble.

The Performance of a Non-Decision Directed Clock Recovery Circuit for 256 QAM Demodulator (256-QAM 복조를 위한 NDD 클럭복원회로의 성능해석)

  • 장일순;조웅기;정차근;조경록
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.1A
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    • pp.27-33
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    • 2000
  • Gardner’s algorithm is one of the useful algorithm for NDD(Non-Decision Directed) symbol synchronization in PAM communications. But the algorithm has a weak point such as pattern noises increasing in multi-level PAM. To insert a pre-filter in the algorithm is able to reduce timing jitter and pattern noise. In this paper, we analyze statistical properties of NDD algorithm to find an optimal parameter of the pre-filter for improving timing jitter and PLL locking. As a simulation result, optimum value of pre-filter parameter, $\beta$, is 0.3 and 0.5 at the roll off factor of the channel, $\alpha$, is 0.5 and 1.0, respectively. Optimum parameters of the pre-filter for clock synchronization of all-digital 256-QAM demodulator is shown in the results.

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Integer Frequency Offset Estimation using PN Sequence within Training Symbol for OFDM System (PN 시퀀스의 위상추적을 통한 Orthogonal Frequency Division Multiplexing 신호의 정수배 주파수 옵셋 추정)

  • Ock, Youn Chul
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.6
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    • pp.290-297
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    • 2014
  • The synchronization of OFDM receiver is consisted of symbol timing offset(STO) estimation in time domain and carrier frequency offset(CFO) estimation in frequency domain. This paper proposes new algorithm for correcting the integer CFO after we have done correcting the STO and partial CFO. ICFO must be corrected, since the ICFO lead to degrade bit error rate(BER) of demodulation performance. The PN sequence has information which is subcarrier order since the modified PN sequence, length is same subcarrier, is used in this paper and is modulated each subcarrier by each chip. Thus the receiver track phase of PN sequence after FFTin order to find the subcarrier frequency offset. The proposed algorithm is faster and more simple than convenient methode as measuring carrier energy.

Design and Implementation of Baseband Modem Receiver for MIMO-OFDM Based WLANs (MIMO-OFDM 기반 무선 LAN 시스템을 위한 기저대역 모뎀 수신부 설계 및 구현)

  • Jang, Soo-Hyun;Roh, Jae-Young;Jung, Yun-Ho
    • Journal of Advanced Navigation Technology
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    • v.14 no.3
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    • pp.328-335
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    • 2010
  • In this paper, an efficient algorithm and area-efficient hardware architecture have been proposed for $2{\times}2$ MIMO-OFDM based WLAN baseband modem with two transmit and two receive antennas. To enhance the performance of the receiver, the efficient timing synchronization algorithm and symbol detector based on MML algorithm are presented. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate, the complexity of the proposed architecture is dramatically decreased. The proposed area-efficient hardware design was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. As a result, the complexity of the proposed modem receiver is reduced by 56% over the conventional architecture.

A Synchronization Technique for OFDM-based Full Duplex Relays with Frequency-domain Feedback Interference Canceller (주파수 영역 궤환 간섭 신호 제거기를 갖는 OFDM 기반 전이중 릴레이를 위한 동기화 기법)

  • Yoo, Hyun-Il;Woo, Kyung-Soo;Park, Chang-Hwan;Kim, Jae-Kwon;Jung, Sung-Yoon;Cho, Yong-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.6A
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    • pp.468-475
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    • 2009
  • In OFDM-based Full Duplex Relays (FDR) with Decode and Forward (DF) scheme, an interference cancellation technique in the frequency domain is more efficient than the one in the time domain. However, an Inter-Symbol Interference (ISI) and Inter-Carrier Interference (ICI) may occur due to the timing mismatch between the feedback interference signal and the desired signal from Base Station (BS) when the feedback interference cancellation and demodulation are performed in the frequency domain. In this paper, the effects of timing mismatch on the synchronous type and asynchronous type of OFDM-based FDR are analyzed for uplink and downlink cases. Then, synchronization procedure and methods for reducing ISI and ICI in OFDM-based FDR with frequency-domain feedback interference canceller are proposed and verified by computer simulation.

A Study on a Cell search Using PCSSCG in Broadband OFCDM Systems (OFCDM시스템에서 PCSSCG를 이용한 셀 탐색에 관한 연구)

  • Kim Dae-Yong;Choi Kwon-Hue;Park Yong-Wan
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.6 s.348
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    • pp.1-8
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    • 2006
  • In the asynchrous OFCDM(Orthogonal Frequency and Code Division Multiplexing) system, a three-step cell search algorithm is performed for the initial synchronization in the following three steps: OFCDM symbol timing, i.e., Fast Fourier Transform(FFT) window timing is estimated employing guard interval (GI) correlation in the first step, then the frame timing and CSSC (Cell Specific Scrambling Code) group is detected by taking the correlation of the CPICH(Common Pilot Channel) based on the property yeilded by shifting the CSSC phase in the frequency domain. Finally, the CSSC phase within the group is identified in the third step. This paper proposes a modification code(PCSSCG:Patial Cell Specific Scrambling Code Group) of the conventional CPICH based cell search algorithm in the second step which offers MS(Mobile Station) complexity reductions with the nearly same performance. The proposed method is to be compared and verified through the computer simulation.

A Cell Search with Reduced Complexity in a Mobile Station of OFCDM Systems (OFCDM 시스템의 이동국에서의 복잡도 감소 셀 탐색)

  • Kim, Dae-Yong;Park, Yong-Wan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.1
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    • pp.139-149
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    • 2007
  • Asynchronous OFCDM(Orthogonal Frequency and Code Division Multiplexing) systems must have a cell search process necessarily unlike synch개nous systems. this process is hewn initial synchronization and a three-step cell search algorithm is performed for the initial synchronization in the following three steps: OFCDM symbol timing, i.e., Fast Fourier Transform(FFT) window timing is estimated employing guard interval (GI) correlation in the first step, then the frame timing and CSSC(Cell Specific Scrambling Code) group is detected by taking the correlation of the CPICH(Common Pilot Channel) based on the property yielded by shifting the CSSC phase in the frequency domain. Finally, the CSSC phase within the group is identified in the third step. This paper proposes a modification group code with two or three block of the conventional CPICH based cell search algorithm in the second step which offers MS(Mobile Station) complexity reductions. however, the effect of the reduction complexity leads to degradation of the performance therefore, look for combination to have the most minimum degradation. the proposed block type group code with suitable combinations is the nearly sane performance as conventional group code and has a complexity reduction that is to be compared and verified through the computer simulation.