• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.55-61
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• 2007

In this paper, we represent the maximum detection probability formulas of symbol synchronization timing at each received delay signal in multipath channel delay profile in the multiplied correlation and difference type correlated symbol synchronization timing detection method. The computer simulation results show that the correlation symbol timing detection method have maximum detection probability at the lead of received delay signal of highest amplitude, but the difference type of correlation symbol timing detection method always have maximum detection probability at the lead of first received delay signal in the multipath channel models. Using this results, we show the BER characteristics difference between the IEEE802.11a OFDM signals which is obtained in case of the symbol synchronization timing is taken at zero error(perfect) timing position and at -1 sample error symbol timing position from perfect timing position in the multipath channel models regardless the length of channel delay spread.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.44-48
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• 2001

In this paper we describe the design of symbol timing and carrier synchronization algorithms for burst receiver. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use modified Gardner algorithm. And we use decision directed method for carrier phase recovery. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 0.1% of symbol rate.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.487-489
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• 2005

This paper proposes a symbol timing recovery method that is simple in structure and can provide high speed symbol synchronization. Transmitter and receiver are not synchronized in communication systems using digital modulation. Receiver should search the timing variation of transmitter continuously. The proposed timing recovery method searches sample position by comparing previous sample value with next sample value. This method can be applied to digital and optical transceivers with high data rate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.1
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• pp.99-108
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• 1999

In this paper, we propose $\pi$/4 QPSK scheme with block modulation algorithm, which can reduce preamble in order to transmit ATM cell efficiently in the uplink channel of LMDS, and also designed a new carrier recovery circuit which can improve carrier synchronization performance of block demodulation algorithm. The $\pi$/4 QPSK scheme employing the proposed block modulation algorithm achieved efficient frame transmission by making use of a few preamble when carrier synchronization, symbol timing synchronization and slot timing synchronization were performed by burst data of ATM cell in LMDS environment. For performance evaluation of the proposed method, a simulation analyzing the variation of carrier synchronization, symbol timing synchronization and slot timing synchronization using LMDS environment and burst mode condition was executed. In the simulation, the proposed method showed a good performance even though the reduced preamble as a few aspossible when carrier synchronization, symbol timing synchronization and slot timing synchronization is performed.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.187-190
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• 1998

In this paper, a synchronization method of OFDM signals are introduced and its performance is estimated. A proposed method can perform a frame/symbol timing, carrier frequency synchronizations. Reference symbols consist of two duplicate OFDM symbols carrying signals on every sub-carriers. Performances of synchronization under 60GHz millimeter-wave indoor channels are evaluated, which were measured with frequency-sweeping method in common office buildings. A proposed method has improved performances owing to long averaging durations of synchronization metrics in frame/symbol timing, carrier frequency synchronization procedures.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.46-54
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• 2007

In this paper, we introduce the performance of improved symbol timing detection by the superposed difference type symbol timing detection method in the OFDM system. Also, we represent the maximum detection probability of symbol synchronization timing at each received delay signal in multipath channel delay profile in the correlation and difference type symbol timing detection methods. The computer simulation results show that the correlation symbol timing detection method have maximum detection probability at the lead of the nth received delay signal of highest amplitude, but the difference type symbol timing detection method always have maximum detection probability at the lead of the first received delay signal in the channel delay spread of $70nsec{\sim}217nsec$. The simulation results indicate the possibility of the perfect detection of OFDM symbol synchronization timing and it fit well with the results of improved S/N to the eb/n0 and the performance of symbol timing detection of the proposed method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1387-1394
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• 2011

In this paper, a low-area symbol timing offset synchronization structure for WLAN Modem is proposed. Using CSD(Canonic Signed Digit) coefficients and CSS(Common Sub-expression Sharing) technique for the filter implementation, efficient structure for multiplication block can be obtained. Function simulation for proposed structure is done by using the preamble with timing offset. Through Verilog-HDL coding and synthesis, it is shown that the proposed symbol timing offset synchronization structure can be implemented with low-area semiconductor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.189-194
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• 2007

This paper derives and computes the detection probability of timing synchronization in an orthogonal frequency division multiplexing (OFDM) system encountered with a multipath Rayleigh fading channel and imperfect noise estimation. The timing synchronization scheme using a simple repeated constant amplitude zero auto-correlation (CAZAC) training symbol and correlation techniques is adopted. With this provision, we focus on the numerical analysis for OFDM timing synchronization scheme employing a preadvancement technique to reduce the inter-symbol interference (ISI). For measuring system performance, the detection performance derived in the considered system is presented in a multipath Rayleigh fading channel.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.86-89
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• 1999

In this paper, we propose a new architecture of the fast symbol timing synchronization system which has some shared hardware blocks in order to reduce the hardware complexity. The proposed system consists of received power detector, correlation power detector using shared complex moving adders, and 2-step peak detector. Our system has detected FFT starting point within three Symbols using first two reference symbols of the frame in wireless ATM system. The new architecture was designed and simulated using VHDL. Our proposed architecture also detects a correct symbol timing synchronization within three symbols under a multi-path fading channel.