Proceedings of the Korea Electromagnetic Engineering Society Conference (한국전자파학회:학술대회논문집)
- 2001.11a
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- Pages.44-48
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- 2001
Design of burst receiver with symbol timing and carrier synchronization
심벌동기와 반송파동기를 가진 버스트 수신기의 설계
Abstract
In this paper we describe the design of symbol timing and carrier synchronization algorithms for burst receiver. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use modified Gardner algorithm. And we use decision directed method for carrier phase recovery. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 0.1% of symbol rate.
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