• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.34-41
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• 1998

In this paper, we evaluate synchronization techniques suitable for high-speed ATM satellite communications with a transmission rate of 155Mbit/s, and propose optimal algorithms that improve the tracking performance, where QPSK is selected for a modulation scheme, and the receiver is operated in burst mode. Based on these asumptions, we proposed modified algorithms and architectures for automatic frequency control(AFC), carrier recovery(CR), and symbol timing recovery(STR) for burst acquisition. Analysis is performed under AWGN environments with respect to the number of required symbol, steady-state stability, and hardware implementation for the proposed algorithms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.307-310
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• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.10C
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• pp.1017-1026
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• 2005

In burst OFDM system, the frame synchronization should be performed first for the acquisition of received frame and the estimation of the correct FFT-window position. The conventional frame synchronization algorithms using design features of the preamble symbol, the repetition pattern of the OFDM symbol by pilot sub-carrier allocation rule and Cyclic Prefix(CP), has difficulty in the detection of precise frame timing because its correlation characteristics would increase and decrease gradually. Also, the algorithm based on the correlation between the reference signal and the received signal has performance degradation due to frequency offset. Therefore, we adopt a differential correlation method that is robust to frequency offset and has the clear peak value at the correct frame timing for frame synchronization. However, performance improvement is essential for differential correlation methods, since it usually shows multiple peak values due to the repetition pattern. In this paper, we propose an enhanced frame synchronization algorithm based on the differential correlation method that shows a clear single peak value by using differential correlation between samples of identical repeating pattern. We also introduce a normalization scheme which normalizes the result of differential correlation with signal power to reduce the frame timing error in the high speed mobile channel environments.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.53-58
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• 2007

OFDM (orthogonal frequency division multiplexing) is an effective modulation technique for high speed transmission over fading channels. However, it has a high bit error rate in the receiver if there is an error on frame synchronization because of phase rotation. A coherent OFDM system has to acquire exact timing synchronization of fraction and integer sampling positions. When a sampling offset exist the performance of a receiver will be degraded severely. In this paper, we propose an algorithm that acquires the fractional sampling offset in OFDM systems. This scheme compares the channel impulse responses with the early and late sampled signals having 0.5 sample offset from the estimated sampling positions by correlation with the received and training samples. Its performance is verified by computer simulations in multipath channels.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1042-1046
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• 2011

In this paper, we analyze the STO (Symbol Timing Offset) problem in conventional ZP-OFDM (Zero Padding-Orthogonal Frequency Division Multiplexing) systems and propose a robust ZP-OFDM system with bi-directional overlap-add scheme to overcome the problem. The proposed ZP-OFDM system is able to preserve the orthogonality between subcarriers and reduce the interference from other ZP-OFDM symbols due to the BOA scheme, which exploits both ZP intervals of the previous and the current ZP-OFDM symbols, even though serious STOs result from inaccurate symbol timing synchronization. Simulation results verify that the proposed ZP-OFDM system is superior to the conventional ZP-OFDM system.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.4 no.1
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• pp.7-13
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• 2005

In this paper, we propose the time synchronization module on fiber optic repeater to use optic line delay for obtaining time synchronization between up-link and down-link, in the 2.3 GHz WiBro network using TDD/OFDM (Time Division Duplex/Orthogonal Frequency Division Multiplexing) Generally, when we use fiber optic repeater to remove the shade area, it occurs transmission delay which is caused by optic transmission between RAS (Radio Access Station) and fiber optic repeater and inner delay of fiber optic repeater. Because the WiBro system is adopting a TOO method and there exists the difference of switching time which is caused by these delay between up-link and down-link, it occurs ISI (Inter Symbol Interference), ICI (Inter Carrier Interference). These interference results in the reduction of the coverage. And the inconsistency between Up-Link and Down-Link switching time maybe gives rise to the interruption of communication. In order to prevent these cases, we propose synchronization module using analog optic line delay as the one of synchronizing up-link and down-link. And we propose the consideration factor for the designing time synchronization module and the feature of optic line of analog method. The measurement result of optic line time synchronization module of structure proposed is as follows, the delay error of $0.5{\mu}g$ and the insertion loss value below maximum 4.5dB in range of $0{\sim}40{\mu}s$. These results fully meet the specification of WiBro System.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.120-130
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• 2009

In this paper, we propose a receiver structure for frequency synchronization in OFDMA (Orthogonal Frequency Division Multiple Access) system which is considered as 3GPP LTE(Long Term Evolution) downlink. In general, OFDMA frequency synchronization consists of two parts: coarse synchronization and fine synchronization. We consider P-SCH (Primary-Synchronization Channel) and CP (Cyclic Prefix) of OFDMA symbol for coarse synchronization and fine synchronization, respectively. The P-SCH signal has two remarkable disadvantages that it does not have sufficiently many sub-carriers and its differential correlation characteristic is not good due to ZC (Zadoff Chu) sequence-specific property. Hence, conventional frequency synchronization algorithms cannot obtain satisfactory performance gain. In this paper, we propose a modified differential correlation algorithm to improve performance of the coarse frequency synchronization. Also, we introduce an effective PLL (Phase Locked Loop) structure to guarantee stable performance of the fine frequency synchronization. Simulation results verify that the proposed algorithm has superior performance to the conventional algorithms and the 2nd-order PLL is effective to track the fine frequency offset even in high mobility.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.905-912
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• 2007

This paper proposes an efficient estimation and compensation scheme of IQ imbalance for OFDM-based WLAN systems in the presence of symbol timing error. Since the conventional scheme assumes perfect time synchronization, the criterion of the scheme used to derive the estimation of IQ imbalance is inadequate in the presence of the symbol timing error and the system performance is seriously degraded. New criterion and compensation scheme considering the effect of symbol timing error are proposed. With the proposed scheme, the IQ imbalance can be almost perfectly eliminated in the presence of symbol timing error. The bit error rate performance of the proposed scheme is evaluated by the simulation. In case of 54 Mbps transmission mode in IEEE 802.11a system, the proposed scheme achieves a SNR gain of 4.3dB at $BER=2{\cdot}10^{-3}$. The proposed compensation algorithm of IQ imbalance is implemented using Verilog HDL and verified. The proposed IQ imbalance compensator is composed of 74K logic gates and 6K bits memory from the synthesis result using 0.18um CMOS technology.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.203-206
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• 2005

This paper presents a design experience of supervisory control system for agile and intelligent manufacturing(AIM). For effectively program job instructions, a Petri net-type graphical language is proposed and it can be applied to a various task such as concurrency and synchronization. PGL is consisted of PGL editor, PGL analyzer and PGL translator; PGL editor generates a job instruction program using graphic symbol. PGL analyzer prevents a deadlock or resource allocation of unit cell. PGL translator transfers to adequate sequential job commands of each unit cell.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.857-860
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• 1999

It is made possible a removal of the preamble for carrier recovery and symbol-timing recovery by storing a burst in memory with low overhead QPSK demodulation and this demodulation method also effects frame efficiency improved by processed synchronization performance. In this paper, we have proposed that new algorithm for arc-tangent look-up table which transform the input I, Q data by phase. This I, Q data plays an important role in demodulation and makes demodulator with low-overhead by storing a burst in memory. To evaluate proposed new algorithm and symbol-timing recovery method, function simulation and timing verification have been done by using synopsys VHDL tool.