• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.2
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• pp.42-48
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• 2005

A DC-DC converter is being widely used for various household appliances and for industry applications. The DC-CC converter is powered from single battery, and the voltage is varied according to the purpose. In the vehicle, various accessories whose electric power is different are being un4 Thus, plural number of DC-DC converter should be provided, so these situations bring complicated circuits, and accordingly, higher cost. Under such backgrounds, in this paper, we propose a novel buck-boost chopper circuit with simply configuration which can supply to two or more different output loads. The propose chewer circuit can control output voltages by controlling duty ratio by using typically two switching devices, which is composed by single boost-switch and single buck-switch. The output voltage can be controlled widely. A few modified circuits developed from the fundamental circuit are represented including the general multi-load circuit. And all this merits and appropriateness was proved by computer simulation and experience.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.107-112
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• 2015

A smart phone and the number of wireless terminals are mobile-to the nature of the AP mobility are many call transfer between wireless terminals and AP (Access Point). Each wireless terminal that is the call processing process for each is relatively large to cause the wireless traffic, and a factor that inhibits the efficient use of the radio band on the AP. In this paper, we use the power intensity threshold and threshold timer of the AP received by the mobile station to reduce the amount of switching traffic between the AP's cause and traffic generation factors between the wireless device and the AP that can effectively utilize the radio traffic from the AP the measures proposed. The proposed method and the conventional method is improved by simulation to handle the amount of radio traffic from the AP it was confirmed that it is possible to effectively utilize the whole of the radio band.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.3
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• pp.128-133
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• 1998

This paper is study on performance analysis of modulator using direct digital frequency synthesizer of Initial Clock Accumulating Method. It has been generally used for PLL or digital frequency synthesizing method to be synthesizd randomly chosen frequency state. In order to improve disadvantage of two methods, we constructed modulator system using DDFS of Initial Clock Accumulating Method. We also confirmed the coherence frequency hopping state and possibility of phase control. The results obtained from the experiments are as follows; First, the synthesized output frequency is proportional to the sampling frequency, according to index, K. Second, the difference of the gain between the basic frequency and the harmonic frequencies was more than 50 [dB], that is, this means facts that is reduced the harmonic frequency factor. Third, coherence frequency hopping state is confirmed by PN code sequence. Here, we confirmed the proposed method cut switching time, this verify facts that is the best characteristic of the frequency hopping. We also verified the fact that the phase varies as the adder is operated set or reset.

• Journal of IKEEE
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• v.24 no.1
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• pp.319-325
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• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.5
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• pp.136-144
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• 2010

This paper presents the two-switch interleaved active clamp forward converter, which is mainly composed of two active clamp forward converters. Only two switches are required, and each one is the auxiliary switch for the other. So, the circuit complexity and cost are reduced and control is more simple. An additional resonant inductance is employed to achieve ZVS(Zero-Voltage-Switching) during the dead times. Interleaved output inductor currents diminish the voltage and current ripple. Accordingly, the smaller output filter and capacitors lower the converter volume. This research proposed the Two-switch interleaved Active Clamp Forward Converter characteristic. The principle of operation, feature and design considerations is illustrated and the validity of verified through the experiment with a 160[W] based experimental circuit.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.1
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• pp.1-7
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• 1998

Due to the increase in capacity of auxiliary machinery in power plant, the importance of energy saving has been greatly emphasized. If the speed of fans or pumps is controlled in accordance with the variation of load, large electric energy can be saved. Large capacity inverter, 2MVA GTO inverter, has been developed by operating two of 1MVA unit inverters in parallel. The parallel operation of the unit inverter is accomplished through two output transformers of which the secondary windings are connected in series. The system is composed of one control cubicle, one rectifier cubicle and 2 unit inverter cubicles. This inverter system was applied to the sea water lift pump(SLP) driven by a 6.6KV 1500KW induction motor in Seo-Inchon power plant to save the electric energy. The parallel operation of inverters by 180 degrees apart in switching frequency helps to reduce the harmonic components.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.3
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• pp.251-259
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• 2009

In this paper, a contactless power supply using half-bridge series resonant converter that achieves ZVS operation of main switches and ZCS operation of secondary side diodes is proposed. Since the proposed contactless power supply using half-bridge series resonant converter operates with lower switching frequency than the resonant frequency, it can achieve ZCS operation of secondary side diodes due to discontinuous resonant current. And it is also possible to control the converter in narrow frequency range and to obtain high voltage gain, which, in turn, offers low turns ratio for the transformer and high efficiency. Based on the theoretical analysis and simulation results, the 3.15W prototype is built and the final experimental results are described.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.10
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• pp.581-586
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• 2002

To improve the current waveform of diode rectifiers, we propose a new operating principle for the voltage-doubler diode rectifiers. In the conventional voltage-doubler rectifier circuit, relatively large capacitors are used to boost the output voltage, while the proposed circuit uses smaller ones and a small reactor not to boost the output voltage but improve the input current waveform. A circuit design method is shown by experimentation and confirmed simulation. The experimental results of the proposed diode rectifier satisfies the harmonic guide lines. A high input power factor of 97(%) and an efficiency of 98[%] are also obtained. The new rectifier with no controlled switches meet the harmonic guide lines, resulting in a simple, reliable and low-cost at-to dc converters in comparison with the boost-type current-improving circuits. This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance value is changed by the polarity of current or voltage. And this paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit is constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduction and the power factor improvement. Half pulse-width modulated (HPWM) inverter was explained compared with conventional pulse width modulated(PWM) inverter. Proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.9
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• pp.805-811
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• 2016

This paper proposes an estimation algorithm of phase currents of inverter systems with the planar bus bars for brush-less DC (BLDC) motors. The planar bus bar can improve the characteristic of the EMC(Electro-Magnetic Compatibility). In these inverters, a single current sensor of the dc-link measures the sum of a smooth capacitor current and phase currents of brush-less DC motor. Thus, it is essential to extract phase currents from the measured single current to control BLDC motor. Therefore, in this paper, the phase current is estimated by analyzing equivalent circuits of the BLDCM in ON and OFF periods of switching elements. The usefulness of the proposed algorithm is verified through experimental results.