• 제목/요약/키워드: switching activity

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CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint (시간제약 조건하에서 모듈 선택 재사용을 이용한 CPLD 저전력 기술 매핑)

  • Kim, Jae-Jin;Lee, Kwan-Hyung
    • Journal of the Korea Society of Computer and Information
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    • v.11 no.3
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    • pp.161-166
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    • 2006
  • In this paper, CPLD low power technology mapping using reuse module selection under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

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Low-power FFT/IFFT Processor for Wireless LAN Modem (무선 랜 모뎀용 저전력 FFT/IFFT프로세서 설계)

  • Shin Kyung-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.11A
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    • pp.1263-1270
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    • 2004
  • A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz@2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz@2.5-V.

Determinants Affecting Organizational Open Source Software Switch and the Moderating Effects of Managers' Willingness to Secure SW Competitiveness (조직의 오픈소스 소프트웨어 전환에 영향을 미치는 요인과 관리자의 SW 경쟁력 확보의지의 조절효과)

  • Sanghyun Kim;Hyunsun Park
    • Information Systems Review
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    • v.21 no.4
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    • pp.99-123
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    • 2019
  • The software industry is a high value-added industry in the knowledge information age, and its importance is growing as it not only plays a key role in knowledge creation and utilization, but also secures global competitiveness. Among various SW available in today's business environment, Open Source Software(OSS) is rapidly expanding its activity area by not only leading software development, but also integrating with new information technology. Therefore, the purpose of this research is to empirically examine and analyze the effect of factors on the switching behavior to OSS. To accomplish the study's purpose, we suggest the research model based on "Push-Pull-Mooring" framework. This study empirically examines the two categories of antecedents for switching behavior toward OSS. The survey was conducted to employees at various firms that already switched OSS. A total of 268 responses were collected and analyzed by using the structural equational modeling. The results of this study are as follows; first, continuous maintenance cost, vender dependency, functional indifference, and SW resource inefficiency are significantly related to switch to OSS. Second, network-oriented support, testability and strategic flexibility are significantly related to switch to OSS. Finally, the results show that willingness to secures SW competitiveness has a moderating effect on the relationships between push factors and pull factor with exception of improved knowledge, and switch to OSS. The results of this study will contribute to fields related to OSS both theoretically and practically.

Service Failure, Service Recovery Activity and Satisfaction with Online Shopping Channel of Apparel Products (온라인 의류쇼핑에서 서비스 실패 경험 후 쇼핑채널의 회복노력에 따른 채널만족도)

  • Kang, Eun Jung;Lee, Kyu-Hye
    • Journal of Digital Convergence
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    • v.11 no.2
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    • pp.115-125
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    • 2013
  • Unexpected consumer dissatisfaction emerges through rapid growth and expansion of on-line shopping channel. This research focused on the fashion online retail channels' negative aspect caused by service failure which possibly disappointed consumers. We also tried to seek for appropriate service recovery types based on frequently offered recovery types on-line. Data from college students were analyzed. Results indicate that fitting problem, insufficient information, product defect, inventory problem and slow delivery were the main service failure types in apparel e-shopping. Regression analysis identified that among these types, insufficient information, product defect, and slow delivery had significant influence on channel satisfaction after post recovery effort. Results also confirmed significant relationships between channel satisfaction and channel switching. Consumers perceived benefit level causes overall channel satisfaction level to rise while perceived risk leads to lower level of channel satisfaction. Choosing desirable service recovery activities in each service failure situations is necessary in order to raise consumer's channel satisfaction in online apparel shopping.

The effect of private information quality on firm performances (개인정보의 질적 수준이 기업성과에 미치는 영향)

  • Son, Jeyoung;Kang, Inwon
    • International Commerce and Information Review
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    • v.18 no.4
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    • pp.31-54
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    • 2016
  • This study explores the factors that determine the quality of private information and how the subsequent consumption behavior is driven. The aim of the study is to discuss how the firms' collection of private information should be conducted and which factors are crucial to raising firm performances. The empirical test conducted with a sample of 331 online consumers suggest that credibility and skepticism were strongly influenced by website reputation and massive information collection, accordingly. Then, the established credibility and skepticism determined the quality of the provided information, ultimately influencing the subsequent consumption behaviors, which are revisit intention and switching intention. Especially, the falsity of provided information was a strong driver of the consumption behavior, highlighting the importance of the quality of provided information on firm performances.

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Design and FPGA Implementation of FBMC Transmitter by using Clock Gating Technique based QAM, Inverse FFT and Filter Bank for Low Power and High Speed Applications

  • Sivakumar, M.;Omkumar, S.
    • Journal of Electrical Engineering and Technology
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    • v.13 no.6
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    • pp.2479-2484
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    • 2018
  • The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

Estimation of Wage Differentials Caused by the Selection of Preferred Job (입직 과정에서의 희망직장 선택이 임금에 미치는 영향 분석)

  • Choi, Youngsup
    • Journal of Labour Economics
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    • v.25 no.1
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    • pp.97-129
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    • 2002
  • It is well known that the quality of job match has strong influence on the efficient allocation of labor resources in the economy on the macro level and also on the productivity of individual worker. Regarding this point we assumed that the selection of preferred job at the job entry can be interpreted as a subjective indicator of job match quality and tried to estimate the effects of such selection on the wage level. For this purpose we suggested random effects switching regression model and applied this model to the data of the Korea Labor Institute Panel Study from 1998 to 2000. As the results of estimation, we found that there exists large wage differentials at least more than fifty percent caused by such selection. Considering the fact that such wage differentials can not be suitably explained by the traditional reasons of the wage discrimination, we suggest the possibility that there also exists large productivity gap caused by the job mismatch and the necessity of improving the job placement service activity.

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Feasibility Study on Long-Term Continuous Ethanol Production from Cassava Supernatant by Immobilized Yeast Cells in Packed Bed Reactor

  • Liu, Qingguo;Zhao, Nan;Zou, Yanan;Ying, Hanjie;Liu, Dong;Chen, Yong
    • Journal of Microbiology and Biotechnology
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    • v.30 no.8
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    • pp.1227-1234
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    • 2020
  • In this study, yeast cell immobilization was carried out in a packed bed reactor (PBR) to investigate the effects of the volumetric capacity of carriers as well as the different fermentation modes on fuel ethanol production. An optimal volumetric capacity of 10 g/l was found to obtain a high cell concentration. The productivity of immobilized cell fermentation was 16% higher than that of suspended-cell fermentation in batch and it reached a higher value of 4.28 g/l/h in repeated batches. Additionally, using this method, the ethanol yield (95.88%) was found to be higher than that of other tested methods due to low concentrations of residual sugars and free cells. Continuous ethanol production using four bioreactors showed a higher productivity (9.57 g/l/h) and yield (96.96%) with an ethanol concentration of 104.65 g/l obtained from 219.42 g/l of initial total sugar at a dilution rate of 0.092 h-1. Furthermore, we reversed the substrate-feed flow directions in the in-series bioreactors to keep the cells at their highest activity and to extend the length of continuous fermentation. Our study demonstrates an effective method of ethanol production with a new immobilized approach, and that by switching the flow directions, traditional continuous fermentation can be greatly improved, which could have practical and broad implications in industrial applications.

An enhanced VS/VD switching algorithm to support fairly ABR service in ATM (ATM 망에서 공정한 ABR 서비스를 제공하는 확장된 VS/VD 스위칭 알고리즘)

  • 양해권;전광탁
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.4 no.2
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    • pp.313-322
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    • 2000
  • The ATM Forum has been focusing on flow control mechanism for ABR traffic management. The goal of this activity is to efficiently manage the leftover network bandwidth and fairly distribute it among contending ABR VC so that communication links can be optimally utilized. ABR traffic is difficult to predict traffic shape because it has bursts and variable behavior. Also it's sensitive to lose but not to delay. This behavior makes difficult to UPC function in network and cause of congestion in switch, thus performance is degraded. To resolve this problem, various flow control mechanism has been worked in the ATM Forum. Especially, the rate-based flow control mechanism for ABR traffic has been standardized in the ATM Forum, Sept. 1994. Thus, various flow control mechanism has been working which likes EFCI, ER, VS/VD. VS/VD control is superior than existed ER control because it isolate different networks from each other. In this paper, we propose an expanded VS/VD flow control algorithm and compare with existed VS/VD flow control algorithm. Simulation result shows that this algorithm improve a problem in aspect of delay and fairness.

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CLB-Based CPLD Low Power Technology Mapping A1gorithm for Trade-off (상관관계에 의한 CLB구조의 CPLD 저전력 기술 매핑 알고리즘)

  • Kim Jae-Jin;Lee Kwan-Houng
    • Journal of the Korea Society of Computer and Information
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    • v.10 no.2 s.34
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    • pp.49-57
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    • 2005
  • In this paper. a CLB-based CPLD low power technology mapping algorithm for trade-off is proposed. To perform low power technology mapping for CPLD, a given Boolean network has to be represented to DAG. The proposed algorithm consists of three step. In the first step, TD(Transition Density) calculation have to be Performed. Total power consumption is obtained by calculating switching activity of each nodes in a DAG. In the second step, the feasible clusters are generated by considering the following conditions : the number of output. the number of input and the number of OR-terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. The proposed algorithm is examined by using benchmarks in SIS. In the case that the number of OR-terms is 5, the experiments results show reduction in the power consumption by 30.73$\%$ comparing with that of TEMPLA, and 17.11$\%$ comparing with that of PLAmap respectively

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