• Journal of Power Electronics
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• 제11권1호
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• pp.1-9
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• 2011

This paper describes a two quadrant bidirectional soft switching converter for ultra capacitor interface circuits. The total efficiency of the energy storage system in terms of size and cost can be increased by a combination of batteries and ultra capacitors. The required system energy is provided by a battery, while an ultra capacitor is used at high load power pulses. The ultra capacitor voltage changes during charge and discharge modes, therefore an interface circuit is required between the ultra capacitor and the battery. This interface circuit must have good efficiency while providing bidirectional power conversion to capture energy from regenerative braking, downhill driving and the protecting ultra capacitor from immediate discharge. In this paper a fully soft switched two quadrant bidirectional soft switching converter for ultra capacitor interface circuits is introduced and the elements of the converter are reduced considerably. In this paper, zero voltage transient (ZVT) and zero current transient (ZCT) techniques are applied to increase efficiency. The proposed converter acts as a ZCT Buck to charge the ultra capacitor. On the other hand, it acts as a ZVT Boost to discharge the ultra capacitor. A laboratory prototype converter is designed and realized for hybrid vehicle applications. The experimental results presented confirm the theoretical and simulation results.

• Journal of Power Electronics
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• 제15권3호
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• pp.587-601
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• 2015

A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.833-836
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• 1993

A flyback type power converter circuit for switched reluctance motor drives is presented. In this converter circuit, the energy extracted from an off going phase is stored in an additional capacitor. The energy stored is used to either be returned to the source frequently or energize the conducting phase during the conduction interval through the transformer. The additional switch to pass the energy stored in the capacitor to the source or the conducting phase is switched under a relatively low voltage condition. Its switching frequency is relatively high so that the size of the transformer can be reduced. The design guideline for the capacitor and the transformer is described. The effectiveness of the presented converter circuit is compared to other circuits through the analysis and experiment.

• 센서학회지
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• 제25권5호
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• pp.326-332
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• 2016

A novel CMOS temperature sensor with binary output is implemented by using fully differential switched-capacitor circuits for resistorless implementation of the temperature sensor core. Temperature sensing is based on the temperature characteristics of the pn diodes implemented by substrate pnp transistors fabricated using standard CMOS processes. The binary outputs are generated by using the charge-balance principle that eliminates the division operation of the PTAT voltage by the bandgap reference voltage. The chip was designed in a MagnaChip $0.35-{\mu}m$ CMOS process, and the designed circuit was verified using Spectre circuit simulations. The verified circuit was laid out in an area of $950{\mu}m{\times}557 {\mu}m$ and is currently under fabrication.

• 대한전자공학회논문지
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• 제19권6호
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• pp.41-51
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• 1982

본 논문에서는 V[S(voltage inverter switch)를 사용한 SCF(switched capacitor filler)에 있어서 VIS의 비이상적인 동작이 여파기 특성에 미치는 영향을 여파기를 구성하는 각 소자들의 변화로써 분석하는 방법을 제시하였다. 또 위의 결과를 VIS가 없는 SCF의 경우에 응용함으로써 대부분의 SC(switched cavacito.) 회로를 쌍일차(bilinear) 변환된 영역에서 그 등가각로를 쉽게 구할 수 있어 SCF의 분석이 용이하고, 높은동작 주파수를 갖는 SCF를 적은 수의 능동 소자로 구현할 수 있는 방법에 대해 기술하였다. 그리고 저역 통과 여파기와 대역 저지 여파기를 실험하여 그 결과가 이론치와 잘 일치함을 보였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.141-144
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• 2002

Several charge Injection compensation circuits, such as, the dummy transistor circuit, the switched OP-amp circuit, the switched capacitor circuit, were fabricated and the test results were compared. The differences between SPICE simulation results and measurements were within around 10%.

• 센서학회지
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• 제27권1호
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• pp.21-24
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• 2018

A temperature sensor with a binary output was implemented using switched-capacitor circuits in a $0.35-{\mu}m$ CMOS(com-plementary metal-oxide semiconductor) process. The measured temperature exhibited good agreement with the oven temperature after calibration. The measured power consumption was 5.61 mW, slightly lower than the simulated power consumption of 6.63 mW.

• Journal of Power Electronics
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• 제19권3호
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• pp.676-690
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• 2019

This paper presents a switched capacitor (SC) based bidirectional dc-dc converter topology for high voltage gain applications. The proposed converter is able to operate with multiple integral voltage conversion ratios based on user input. The architecture of a user-friendly, inductor-less multi-voltage-gain bidirectional dc-dc converter is proposed in this study. The inductor-less or magnetic-less design of the proposed converter makes it effective in higher temperature applications. Furthermore, the proposed converter has a reduced component count and lower voltage stress across its switches and capacitors when compared to existing SC converters. An output impedance analysis of the proposed converter is presented and compared with popular existing SC converters. The proposed converter is simulated in the OrCAD PSpice environment and the obtained results are presented. A 200 W hardware prototype of the proposed SC converter has been developed. Experimental results are presented to validate the efficacy of the proposed converter.

• Journal of Power Electronics
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• 제16권2호
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• pp.436-446
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• 2016

A novel step-up DC-DC converter with a switched-coupled-inductor-capacitor (SCIC) which successfully integrates three-winding coupled inductors and switched-capacitor techniques is proposed in this paper. The primary side of the coupled inductors for the SCIC is charged by the input source, and the capacitors are charged in parallel and discharged in series by the secondary windings of the coupled inductor to achieve a high step-up voltage gain with an appropriate duty ratio. In addition, the passive lossless clamped circuits recycle the leakage energy and reduce the voltage stress on the main switch effectively, and the reverse-recovery problem of the diodes is alleviated by the leakage inductor. Thus, the efficiency can be improved. The operating principle and steady-state analyses of the converter are discussed in detail. Finally, a prototype circuit at a 50 kHz switching frequency with a 20-V input voltage, a 200-V output voltage, and a 200-W output power is built in the laboratory to verify the performance of the proposed converter.

• 전기학회논문지P
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• 제52권4호
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.