• Title/Summary/Keyword: switch mode power supply

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Design of a Low-Power 8-bit 1-MS/s CMOS Asynchronous SAR ADC for Sensor Node Applications (센서 노드 응용을 위한 저전력 8비트 1MS/s CMOS 비동기 축차근사형 ADC 설계)

  • Jihun Son;Minseok Kim;Jimin Cheon
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.16 no.6
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    • pp.454-464
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    • 2023
  • This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

Reliability improvement methods of AF track circuits for the train control system (열차내 연산시스템용 AF궤도회로 신뢰성향상 방안 연구)

  • Park, Jae-Young
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.10
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    • pp.4762-4767
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    • 2012
  • The AF track circuit that detecting train position and transmitting various train control data for DTG to the train on-board is composed of single operation system. If a failure occurs on this system, the driver should be operate the train by manually until the system is restored, because the system cannot control switch machines and signals by automatically. In this process the human error affects to the train delay, collision, derailment and critical safety accident. Therefore, this document has analyzed the effects that each failure mode influences on system and train, and quantified the failure valuation point and class. Basis on this quantified analysis result, MTBF increased and MTTR decreased and failure number also decreased by adopting the independent installation of power supply, the replacement of defected capacitors, the installation of resister cooling system and the improvement of maintenance methods. And the failure factors of AF track circuits were decreased by conducting the preventive maintenance which is a quantitative way of maintenance system by experience.

A Study on the Design of Binary to Quaternary Converter (2진-4치 변환기 설계에 관한 연구)

  • 한성일;이호경;이종학;김흥수
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.3
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    • pp.152-162
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    • 2003
  • In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

Design of Variable Gain Low Noise Amplifier with Memory Effects Feedback for 5.2 GHz Band (5.2 GHz 대역에서 동작하는 기억 기능 특성을 갖는 궤환 회로를 이용한 변환 이득 저잡음 증폭기 설계)

  • Lee, Won-Tae;Jeong, Ji-Chai
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.1
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    • pp.53-60
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    • 2010
  • This paper presents a novel gain control system composed of a feedback circuit, Two stage Low Noise Amplifier (LNA) using 0.18 um CMOS technology for 5.2 GHz. The feedback circuit consists of the seven function blocks: peak detector, comparator, ADC, IVE(Initial Voltage Elimination) circuit, switch, storage, and current controller. We focus on detecting signal and designing storage circuit that store the previous state. The power consumption of the feedback circuit in the system can be reduced without sacrificing the gain by inserting the storage circuit. The adaptive front-end system with the feedback circuit exhibits 11.39~22.74 dB gain, and has excellent noise performance at high gain mode. Variable gain LNA consumes 5.68~6.75 mW from a 1.8 V supply voltage.

Design and Analysis of a 12 V PWM Boost DC-DC Converter for Smart Device Applications (스마트기기를 위한 12 V 승압형 PWM DC-DC 변환기 설계 및 특성해석)

  • Na, Jae-Hun;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.6
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    • pp.239-245
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    • 2016
  • In this study, a 12 V PWM boost converter was designed with the optimal values of the external components of the power stage was well as the compensation stage for smart electronic applications powered by a battery device. The 12 V boost PWM converter consisted of several passive elements, such as a resistor, inductor and capacitor with a diode, power MOS switch and control IC chip for the control PWM signal. The devices of the power stage and compensation stage were designed to maintain stable operation under a range of load conditions as well as achieving the highest power efficiency. The results of this study were first verified by a simulation in SPICE from calculations of the values of major external elements comprising the converter. The design was also implemented on the prototype PCBboard using commercial IC LM3481 from Texas Instruments, which has a nominal output voltage of 12 V. The output voltage, ripple voltage, and load regulation with the line regulation were measured using a digital oscilloscope, DMM tester, and DC power supply. By configuring the converter under the same conditions as in the circuit simulation, the experimental results matched the simulation results.

Implementation of AC Direct Driver Circuit for Ultra-slim LED Flat Light System (초슬림 LED 면조명 기구용 교류 직결형 구동 회로 구현)

  • Cho, Myeon-Gyun;Choi, Hyo-Sun;Yoon, Dal-Hwan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.9
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    • pp.4177-4185
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    • 2012
  • LEDs are becoming the most suitable candidate replacing traditional fluorescent lamps because of its eco-friendly characteristics. LEDs are also actively used to design green building system and to make outdoor billboard as a back-light system due to its high energy efficiency. In this paper, we have developed AC direct driver for $12{\times}12$ FLB(flexible LED board) and LED flat light without SMPS. It has LID-PC-R101B driver IC that can support the high power factor and be composed of LED switching circuit in group. Also, an elaborate system designs can guarantee a high luminous efficiency, a high reliability and a low power consumption. The proposed FLB has the ultra slim shape of $450{\times}450$ mm, width of 4 mm and weight of 280 g. In the end, we have developed a prototype of FLB for billboard and flat light for room lighting with AC direct driver iposrder to verify the performance of the proposed system.