• 제목/요약/키워드: switch cell

검색결과 353건 처리시간 0.023초

공유 버스와 공유 메모리 스위치를 이용한 멀티캐스트 ATM 스위치 구조 (A Multicast ATM Switch Architecture using Shared Bus and Shared Memory Switch)

  • 강행익;박영근
    • 한국통신학회논문지
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    • 제24권8B호
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    • pp.1401-1411
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    • 1999
  • 멀티미디어 서비스의 증가에 따라 멀티캐스팅(Multicasting)은 ATM 스위치 디자인에 있어 중요성을 더해가고 있다. 기존의 다단 연결 구조에서 멀티캐스트에 의한 트래픽 팽창의 문제를 해결하기 위해 본 논문에서는 고속의 버스와 공유 메모리 스위치를 이용한 멀티캐스트 스위치를 제안한다. 고속의 시분할 버스를 연결 매체로 사용하며 공유 메모리 스위치를 단위 모듈로 하는 구조를 채택하여 용이한 포트 확장성을 제공한다. 트래픽 중재 기법을 사용하여 내부 블러킹을 없애며, 시뮬레이션을 통해 데이터 처리율이나 셀지연 측면에서의 스위치 성능을 확인한다.

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단조 버퍼링 방식을 이용한 Banyan형 ATM 스위치의 성능평가 (The Performance of Banyan Type ATM Switch using Monotonic Buffering Scheme)

  • 김범식;우찬일;신인철
    • 한국산업정보학회:학술대회논문집
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    • 한국산업정보학회 1997년도 추계학술대회 발표논문집:21세기를 향한 정보통신 기술의 전망
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    • pp.147-161
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    • 1997
  • In the future, the performance of B-lSDN offering the multimedia and a various service depends on the performance of switch that is the important factor consisting of network. Bufferless banyan network consisted of MIN(multistage interconnection network) selected for- the fabric of ATM switch and has a limitation of performance because of blocking. Input buffered banyan networks with FIFO(first-in first-out) buffering scheme for the reduction of blocking and the cell bypass queueing theory for the reduction of HOL(head of line) blocking were seperately compared of the performance of switch. Specially input buffered banyan networks were applied monotonic buffering scheme that was proposed. As a result of simulation, Buffered Banyan Network with cell bypass queueing theory showed better performance than FIFO type input buffered Banyan network. Monotonic increase buffering scheme showed better performance than Monotonic decrease buffering scheme.

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New Zero-Current-Transition (ZCT) Circuit Cell Without Additional Current Stress

  • Kim Chong-Eun;Choi Eun-Suk;Youn Myung-Joong;Moon Gun-Woo
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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    • pp.294-298
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    • 2003
  • In this paper, the new zero-current-transition (ZCT) circuit cell is proposed. The main switch is turned-off under the zero current and zero voltage condition, and there is no additional current stress and voltage stress in, the main switch and the main diode. The Auxiliary switch is turned-off under the zero voltage condition, and the main diode is turned-on under the zero voltage condition, The resonant current required to obtain the ZCT is small and regenerated to the input voltage source. The operational principles of the boost converter integrated with the proposed ZCT circuit cell is analyzed theoretically and verified by the simulation and experimental result. Index terms - zero-current-transition (ZCT), zero-current- switching (ZCS), zero-voltage-switching (ZVS)

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멀티캐스트 환경에서 향상된 처리율을 갖는 공유 다중 버퍼 ATM스위치의 VLSI 설계 (VLSI design of a shared multibuffer ATM Switch for throughput enhancement in multicast environments)

  • Lee, Jong-Ick;Lee, Moon-Key
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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    • pp.383-386
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    • 2001
  • This paper presents a novel multicast architecture for shared multibuffer ATM switch, which is tailored for throughput enhancement in multicast environments. The address queues for multicast cells are separated from those for unicast cells to arbitrate multicast cells independently from unicast cells. Three read cycles are carried out during each cell slot and multicast cells have chances to be read from shared buffer memory(SBM) in the third read cycle provided that the shared memory is not accessed to read a unicast cell. In this architecture, maximum two cells are queued at each fabric output port per time slot and output mask choose only one cell. Extensive simulations are carried out and it shows that the proposed architecture has enhanced throughput comparing with other multicast schemes in shared multibuffer switch architecture.

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이동 통신 네트워크에서의 듀얼 호밍 셀 스위치 할당을 위한 유전자 알고리듬 (A Genetic Algorithm for Assignments of Dual Homing Cell-To-Switch under Mobile Communication Networks)

  • 우훈식;황선태
    • Journal of Information Technology Applications and Management
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    • 제13권2호
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    • pp.29-39
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    • 2006
  • There has been a tremendous need for dual homing cell switch assignment problems where calling volume and patterns are different at different times of the day. This problem of assigning cells to switches in the planning phase of mobile networks consists in finding an assignment plan which minimizes the communication costs taking into account some constraints such as capacity of switches. This optimization problem is known to be difficult to solve, such that heuristic methods are usually utilized to find good solutions in a reasonable amount of time. In this paper, we propose an evolutionary approach, based on the genetic algorithm paradigm, for solving this problem. Simulation results confirm the appropriateness and effectiveness of this approach which yields solutions of good quality.

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New Zero-Current-Transition (ZCT) Circuit Cell Without Additional Current Stress

  • Kim, C.E.;Park, E.S.;G.W. Moon
    • Journal of Power Electronics
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    • 제3권4호
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    • pp.215-223
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    • 2003
  • In this paper, a new zero-current-transition (ZCT) circuit cell is proposed. The main switch is turned-off under the zero current and zero voltage condition, and there is no additional current stress and voltage stress in the main switch and the main diode, respectively. The auxiliary switch is turned-off under the zero voltage condition, and the main diode is turned-on under the zero voltage condition. The resonant current required to obtain the ZCT condition is relatively small and regenerated to the input voltage source. The operational principles of a boost converter integrated with the proposed ZCT circuit cell are analyzed and verified by the simulation and experimental results.

ATM 교환기내 Ethernet Switch를 이용한 IPC망 구현 (Design and Implementation of IPC Network using Ethernet Switch In ATM)

  • 김법중;나지하;오정훈;안병준
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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    • pp.255-258
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    • 2000
  • This paper presents an Interprocessor Communication Network(IPC net) in ATM switching system. In order to supply stable and independent path for processor communication, additional network i.e., Ethernet, is suggested. An Ethernet switch centered on Ethernet binds each processor into a work range. IPC net proposed in this paper assures end-to-end inter-processor connection, uniform 100Mbps Ethernet bandwidth and enhanced user cell throughput of ATM switch with minimum Ethernet supporting block integrated into ATM system

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준 공유 출력 버퍼형 스위치 구조 (Quasi-Shared Output Buffered Switch)

  • 남승엽;성단근;안윤영
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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    • pp.283-286
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    • 2000
  • One major drawback of conventional output buffered switches is that the speed of writing cells into output buffer should be N times faster than input link speed. This paper proposes a new output buffer switch that divides one output buffer into several buffers and virtually shares the divided buffers by using a distributor. The proposed switch makes it possible to reduce the memory speed. The proposed switch is evaluated in terms of the average cell latency compared with the input buffered switches which use the arbitration alogorithms, i.e., iSLIP or wrapped wave front arbiter(WWFA).

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완전 결합형 ATM 스위치 구조 및 구현 (II부 스위치 엘리먼트 ASIC화 및 스위치 네트워크 구현에 대하여) (Structure and Implementation of Fully Interconnected ATM Switch (Part II : About the implementation of ASIC for Switching Element and Interconnected Network of Switch))

  • 김경수;김근배;박영호;김협종
    • 한국통신학회논문지
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    • 제21권1호
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    • pp.131-143
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    • 1996
  • In this paper, we propose the improved structure of fully interconnected ATM Switch to develop the small sized switch element and represent practical implementation of switch network. As the part II of the full study about structure and implementation of fully interconnected ATM Switch, this paper especially describes the implementation of an ATM switching element with 8 input port and 8 output port at 155 Mbits/sec each. The single board switching element is used as a basic switching block in a small sized ATm switch for ATM LAN Hub and customer access node. This switch has dedicated bus in 12 bit width(8 bit data + 4 bit control signal) at each input and output port, bit addressing and cell filtering scheme. In this paper, we propose a practical switch architecture with fully interconnected buses to implement a small-sized switch and to provide multicast function withoutany difficulty. The design of switching element has become feasible using advanced CMOS technology and Embedded Gate Array technology. And, we also represent Application Specific Integrated Circuit(ASIC) of Switch Output Multiplexing Unit(SOMU) and 12 layered Printed Circuit Board for interconnection network of switch.

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Nd:YAG Laser를 위한 포켓셀 Q-스위치특성 연구 (A study on the characteristic of Pockel cell Q-switch for Nd:YAG laser)

  • 김휘영
    • 디지털콘텐츠학회 논문지
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    • 제10권2호
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    • pp.199-207
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    • 2009
  • Q-스위칭은 셔터나 다른 광학소자를 레이저 광 공진기 내에 넣어 광이 공진기 내에서 발진하는데 손실을 유발하고, 충분한 반전분포가 활성 매질 내에서 생성되면 순간적으로 셔터를 열어 공진기 내에 축적된 에너지가 매우 강한 빛으로 방출되게 하는 것이다. 이와 같이 Q-스위칭은 레이저 공진기의 Q--factor를 감소시켰다가 갑자기 증가시키는 것이다. 레이저 Q-스위칭의 방법에는 mechanical switching 방법, electro-optic switching 방법, switching by saturable absorber 방법, acousto-optic switching 방법 등 크게 4가지가 쓰이고 있다. 이들 중 전기광학적인 효과에 의한 전기적인 전환은 짧은 펄스폭의 Q-스위칭 펄스를 생성할 수 있기 때문에 널리 사용되고 있다. 따라서, 전기광학효과의 특성을 가진 Pockel cell은 Q--switch로 사용하기 적합한 것으로 알려져 있다. 본 연구에서는 포켈스 셀 Q-스위치용 구동 장치를 스위칭 소자인 FET와 PIC 마이크로프로세서 및 펄스 트랜스로 설계, 제작하고, 펄스형 Nd:YAG 레이저 시스템에 적용하여 Q-스위치의 동작 특성을 조사, 연구하였다. 또한, 이 Q-스위치를 통하여 출력된 Nd:YAG 레이저 빔의 측정치를 이론적 계산에 의해 구해진 예상치와 비교하여 Q-스위칭 된 레이저 빔의 특성을 분석하였다.

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