• Journal of Power Electronics
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• v.5 no.2
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• pp.99-103
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• 2005

In this paper, a novel circuit topology of a three-winding coupling inductor-assisting a high-frequency PWM boost chopper type DC-DC power converter with a high boost voltage conversion ratio and low switch voltage stress is proposed for the new energy interfaced DC power conditioner in solar photovoltaic and fuel cell generation systems. The operating principle in a steady state is described by using its equivalent circuits under the practical condition of energy processing of a lossless capacitive snubber. The newly-proposed power MOSFET boost chopper type DC-DC power converter with the three-winding coupled inductor type transformer and a single lossless capacitor snubber is built and tested for an output power of 500W. Utilizing the lower voltage and internal resistance power MOSFET switch in the proposed PWM boost chopper type DC-DC power converter can reduce the conduction losses of the active power switch compared to the conventional model. Therefore, the total actual power conversion efficiency under a condition of the nominal rated output power is estimated to be 81.1 ％, which is 3.7％ higher than the conventional PWM boost chopper DC power conversion circuit topology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.394-397
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• 2003

In this paper, we describe the implementation of high performance buffer manager that is used in an advanced input-queued switch fabric. The designed buffer manager provides wire-speed cell/packet routing with low cost and tolerates the transmission pipeline latency of request and grant data. The buffer manager is implemented in a FPGA chip and supports the speed of OC-48c, 2.5Gbps per port.

• Journal of Power Electronics
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• v.7 no.2
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• pp.109-117
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• 2007

In this paper, a novel proposal for a utility-interactive three-phase soft commutation sinewave PWM power conditioner with an auxiliary active resonant DC-link snubber is developed for fuel cell and solar power generation systems. The prototype of this power conditioner consists of a PWM boost chopper cascaded three-phase power conditioner, a single two-switch auxiliary resonant DC-link snubber with two electrolytic capacitors incorporated into one leg of a three-phase V-connection inverter and a three-phase AC power source. The proposed cost-effective utility-interactive power conditioner implements a unique design and control system with a high-frequency soft switching sinewave PWM scheme for all system switches. The operating performance of the 10 kW experimental setup including waveform quality, EMI/RFI noises and actual efficiency characteristics of the proposed power conditioner are demonstrated on the basis of the measured data.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.63-69
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• 2017

This paper presents a highly efficient power management system for UAV-drones. For free from the battery cell-balancing issue, the proposed system allows the drone to utilize a single-cell Li-Po battery. To realize low-voltage input of 3.7V, the switch-mode step-up DC-DC converter is optimally designed with high power efficiency. The prototype DC-DC converter was implemented with an output voltage of 5V, which will be provided to digital parts of the drone. The power efficiency was measured to be max. 91.3% with low surface temperature. The measured line and load regulations were 0.02V/V and 0.15V/A, respectively. Thanks to the proposed power management system, the available time-to-fly of the drone is expected to be significantly extended in virtue of the enhanced power efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.685-691
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, considering linearity, power consumption, chip area, and glitch energy. The low-glitch switch driving circuit is employed to improve the linearity and the dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core. The prototype DAC is implemented in a 0.35 urn n-well single-poly quad-metal CMOS technology. The measured DNL and INL of the prototype DAC are within $\pm$0.75 LSB and $\pm$1.73 LSB, respectively, and the spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of 2.2 mm ${\times}$ 2.0 mm.

• Journal of the Korea Computer Industry Society
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• v.2 no.9
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• pp.1163-1174
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• 2001

A general goal of the ATM(Asynchronous Transfer Mode) network is to support connections across various networks. ABR service using EPRCA(Enhanced Proportional Rate Control Algorithm) switch controls traffics in ATM network. EPRCA switch, traffic control method uses variation of the ACR(Allowed Cell Rate) to enhance the utilization of the link bandwidth. However, in ABR(Available Bit Rate) service, different treatments are offered according to different RTTs(Round Trip Times) of connections. To improve the above unfairness, this paper presents ABR DELAY mechanism, in which three reference parameters for cell delay are defined, and reflect on the messages of RM(Resource Management) cells. To evaluate our mechanism, we compare the fairness among TCP connections between ABR DELAY mechanism and ABR RRM mechanism. And also we execute simulations on a simple ATM network model where six TCP connections and a background traffic with different RTTs share the bandwidth of a bottleneck link. The simulation results, based on TCP goodput and efficiency, clearly show that ABR DELAY mechanism improves the fairness among TCP connections.

• Journal of information and communication convergence engineering
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• v.4 no.4
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• pp.170-173
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• 2006

Recently, with increasing efficiency of DSC (photo-electrochemical using a nano-particle), The Performance of DSC solar generation system also needs improvement. The approach consists of a Fly-back DC-DC (transfer ratio 1:10) converter to boost the DSC cell voltage to 300VDC. The four switch (MOSFET) inverter is employed to produce 220V, 60Hz AC outputs. High performance, easy manufacturability, lower component count., safety and cost are addressed. Protection and diagnostic features form an important part of the design. Another highlight of the proposed design is the control strategy, which allows the inverter to adapt to the: requirements of the load as well as the power source. A unique aspect of the design is the use of the DSP TMS320LF2406 to control the inverter by current and voltage feed-back. Efficient and smooth control of the: power drawn from the DSC Cell is achieved by controlling the front end DC-DC converter in current mode.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.19-26
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• 2002

This paper propose the queue structure of cell buffering in the output buffer of ATM switch for the traffic with the different QoS. The proposed queue structure can minimize the cell loss ratio of bursty traffic, maximize the queue utilization through the sharing of real-time queue and non-real-time queue. To evaluate the proposed queue structure, we compare the CLP and cell average delay of the proposed queue and fixed queue using the bursty traffic patterns.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.696-705
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• 2002

This paper presents a new copy network for multicast ATM switches. Many studies have been carried out up to date since the proposition of Lee's copy network. However, the overflows and cell conflicts within the switch have still been raised a problem in argument. In order to reduce those problems, we proposed a 3-dimensional multicast switching architecture which has shared buffers in this paper. The proposed architecture can reduce the overflows and cell conflicts through multiple paths and output ports even in the high load environments. Also, we proposed a cell splitting algorithm which handles the cell in the case of large fan-out, and a copy network to increase throughput by expanding the Lee's Broadcast Banyan Network(BBN). Cell copy uses the Boolean interval splitting algorithm and the multicast pattern of the cells according to the self-routing characteristics of the network. In the proposed copy network, we improve the problems such as overflow, cell splitting of large fanout, cell conflicts, etc., which were still existed in the Lee's network. The results of performance evaluation by computer simulation show that the proposed scheme has better throughput, cell loss rate and cell delay than the conventional method.