• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1393-1398
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• 2003

In this paper, we propose a new switch architecture with one schedule at k-time slots, which k means the allocated time slots for each schedule. A conventional switch system uses a single time slot per each schedule but the proposed switch system uses multiple time slots per each schedule. Both the conventional switch md the proposed switch have same throughput but our switch system occupies multiple cell time slots per each schedule and hence can be implemented in scheduler of simple circuitry compared to the conventional switch. The proposed scheduling method for switch system will be applicable in switch system with high-speed data link rate.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.946-949
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• 2001

This paper proposes a new zero-current switching (ZCS) pulse-width modulation (PWM) switch cell that has no additional conduction loss of the main switch. In this cell, the main switch and the auxiliary switch turn on and turn off under zero current condition. The diodes commutate softly and the reverse recovery problems are alleviated. The conduction loss and the current stress of the main switch are minimized, since the resonating current for the soft switching does not flow through the main switch. Based on the proposed ZCS PWM switch cell, a new family of dc to dc PWM converters is derived. The new family of ZCS PWM converters is suitable for the high power applications employing IGBTs. Among the new family of dc to dc PWM converters, a boost converter was taken as an example and has been analyzed. Design guidelines with a design example are described and verified by experimental results from the 2.5 kW prototype boost converter operating at 40kHz.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.169-175
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• 1998

There is a shared multibuffer method which can preventing HOL blocking in ATM switch. However, the system still has a problem that reduces the performance of the system because of the cell loss. Therefore, in this paper, preventing of cell loss in non-contentional shared multibuffer switch is suggested. To prevent cell loss, a structure is suggested that a cell can be loss in a certain slot time is stored in the dedicated temporary memory so the cell can be transferred in the next slot time. The simulation result of the structure, this suggested system superior performance than the exited system in cell loss rate and throughput.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.92-94
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• 2003

In superconductive digital logic circuits, D2 cells can be used to compose a decoder an important component of an Arithmetic Logic Unit (ALU). In this wor, we simulated D2 cell by using WRspice. D2 cell has one input, one switch input, and two outputs (output1 and output2). D2 cell functions in such way that output1 follows the input and output2 is the complement of the input data, when the switch input is "0, ". However, when there is a switch input "1, " the opposite output signals are generated. In this paper, we optimized a D2 cell by using WRspice, and obtained the minimum margin of 26%. Our optimized D2 cell will play a key role in the ALU fabrication.the ALU fabrication.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.388-391
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• 2000

In this paper a modified ZVZCS(zero-voltage/zero-current switching) commutation cell with minimum additional components which provides soft switching at both turn-on and turn-off of main and auxiliary switches as well as diodes in PWM converters is presented. The proposed soft-switching technique is suitable for not only minority but also majority carrier semiconductor devices. The auxiliary switch of the proposed ZVZCS commutation cell is in parallel with the main switch and therefore there is no current stress on the main switch and diode. The operation principles of the proposed ZVZCS commutation cell are theoretically analyzed using the PWM boost converter topology as an example. Theoretical analysis simulation and experimental results verify the validity of the PWM boost converter topology with the proposed ZVZCS commutatioin cell.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.4
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• pp.183-190
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• 2002

This paper presents an improved Zero Voltage/Zero Current Switching (ZVZCS) commutation cell with minimum additional components, which provides soft switching at both turn-on and turn-off of main and auxiliary switches as well as diodes in a PWM DC/DC converter. The proposed soft-switching technique is suitable for not only minority, but also majority carrier semiconductor devices. The auxiliary switch of the proposed ZVZCS commutation cell is in parallel with the main switch, and therefore, the main switch and the diode are free of currentstress. The operation principles of the proposed ZVZCS commutation cell are theoretically analyzed using the PWM boost converter topology as an example. The validity of the PWM boost converter topology with the proposed ZVZCS commutation cell is verified through theoretical analysis, simulation and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3B
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• pp.209-216
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• 2003

In this paper, we propose ATM switch structure including AAL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of AAL cells which consist of AAL type 1, AAL type 2, AAL type 3/4, and AAL type 5 cells. We propose two switch fabric methods; One supports the AAL type 2 cell processing per input port, the other global AAL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a merit for easy implementation and extensibility. The proposed ATM switch fabric is widely applicable to mobile communication, narrow band services over ATM network and wireless ATM as well as general ATM switching fabric.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.205-208
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• 2002

An existing ATM switch fabric uses VPI(Virtual Path Identifier) and VCI(Virtual Channel Identifier) information to route ATM cell. But AAL type 2 switch which efficiently processes delay-sensitive, low bit-rate data such as a voice routes the ATM cell by using CID(Channel Identification) field in addition to VPI and VCI. In this paper, we research the AAL type 2 switch that performs the process of CPS packet. The Receive unit extracts the CPS packet from the inputted ATM cell. The designed receive unit consists of input FIFO, r)( status table, CAM(Content Addressable Memory), new CID table and partial packet memory. Also the designed receive unit supports the PCI interface with host processor. The receive unit is implemented in Xilinx FPGA and operates at 72MHz.

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.217-219
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• 2005

This paper presents an improved ZCT (Zero-Current-Transition) PWM DC/DC Boost Converter without additional current stress and conduction loss on the main switch during the resonance period of the auxiliary cell. The auxiliary cell consists of a resonance inductor, a resonant capacitor, an auxiliary switch and the Zero-Current-Switching ranges of the main and the auxiliary switch of the proposed converters are entirely achieved by operating the auxiliary cell. Then Improved ZCT soft switching converter will be discussed. Therefore, the proposed converter has a high efficiency. To show the superiority of this converter is verified through the experiment with a 640W, 50kHz prototype converter.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.75-78
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• 1998

In this paper, we propose a new cell discarding and scheduling scheme which reduce cell loss rate by measuring, in real time, the number of discarded cells in the queuing system with a different loss priority for each class of service such that each class of service meets its cell loss rate requirements and reduce average delay rate for the traffic that is sensitive in cell delay in output buffer of the ATM switch. Throughout the computer simulation, the existing scheduling scheme and proposed scheme are compared with respect to cell loss rate and average delay time.