• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 B
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• pp.1243-1247
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• 1996

In this paper, a small PLC system is designed and developed for the distributed building control and fire control system. It uses 8031, a 8-bit micro controller from Intel Inc. The size of the PLC is $7cm{\times}8cm$ and the PLC can accept 4 sensor inputs and drive 4 relay outputs, which operates at 24V. Multiple access of PLC by one host computer is implemented by assigning a unique 10 to each PLC, which ranges from 0 to 126. The operation starts by sending a command packet from host computer to a PLC and the PLC of the same 10 fetches the command packet by comparing the first byte of the command packet with its own 10. The PLC is programmed to perform a various functions and the function is selected by the content of the command byte, which is the second byte of the command packet. The third byte, which is the last byte, is a checksum byte. The checksum byte is the sum of the first byte and the second byte and is used to detect the communication error. Depending on the content of the command byte, PLC performs the desired function and returns the response packet back to the host computer. The response packet is also a three-byte packet, 10 byte, response byte and checksum byte. For the independent operation of PLC without being controlled by the host computer, variable length RULE data packet is sent to PLC. In case the communication line is broken, the PLC perform the independent operation by referencing the RULE data. The applicable areas are; building automation system, distributed factory automation, measurement of temperature of toxic or dangerous area.

• 한국빅데이터학회지
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• 제7권1호
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• pp.75-87
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• 2022

재작업은 제품의 품질 만족을 위해 요구되는 활동으로 제조 현장에서 필수적인 공정이다. 사전에 수행 여부의 파악이 어려운 재작업은 공정시간의 증가 및 제품의 납기 지연으로 이어질 수 있어 이를 고려한 스케줄링이 중요하다. 본 연구에서는 자동차 배관 생산라인인 재작업이 존재하는 유연흐름라인을 대상으로 Dispatching을 통한 평균 흐름시간과 납기지연의 가중합을 최소화하는 스케줄링 연구를 진행하였다. 본 연구에서는 제품별 납기 등 고객 요구와 재작업 및 가공시간 등의 변동성이 존재하는 제조환경에서 Dispatching을 위한 가중치 기반 Dispatching 규칙(WDR)을 제안한다. WDR은 여러 단일 Dispatching 규칙의 가중합으로 구성되며 본 연구는 가중치 탐색을 위해 시뮬레이션 기반 유전알고리즘을 적용하였다. 시뮬레이션 실험을 통해 WDR이 단일 Dispatching 규칙에 비해 우수한 성능을 보임을 확인하였다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• 융합신호처리학회논문지
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• 제6권2호
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• pp.89-94
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• 2005

본 논문에서는 새로운 방법의 Fuzzy PID 제어기를 제안한다. 우선 절대형 디지털 PID 제어기에서 두 가지 문제점이 있다. 첫째는 매 제어 주기마다 많은 데이터의 합을 구해야 하므로 계산시간이 많이 소요되고, 둘째는 이 계산을 위해 이전의 모든 데이터를 보관하고 있어야 되기 때문에 메모리가 많이 필요한 문제점이 있다. 위의 문제점을 개선하기 위해 속도형 디지털 PID 제어기를 사용한다. 제안한 제어기에서는 PID 제어기의 목표 값과 현재 출력 값의 차인 크리스퍼(crisp) 출력 오차를 그대로 사용하지 않고 퍼지추론의 단계는 가지면서 Rule Table은 갖지 않는 특징이 있으며 출력 소속 함수에 두 변수의 관계와 범위에 의해 도식화된 영역에서 삼각형 무게 중심법으로 비퍼지화된 비선형 출력 값을 PID 계수에 인가하는 새로운 Fuzzy PID 제어기를 제안한다.

• 천문학회보
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• 제40권1호
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• pp.44.1-44.1
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• 2015

We present joint constraints on the number of effective neutrino species $N_{eff}$ and the sum of neutrino masses ${\Sigma}m_{\nu}$, based on a technique which exploits the full information contained in the one-dimensional Lyman-${\alpha}$ forest flux power spectrum, complemented by additional cosmological probes. In particular, we obtain $N_{eff}=2.91{\pm}0.22$ (95% CL) and ${\Sigma}m_{\nu}$ < 0.15 eV (95% CL) when we combine BOSS Lyman-${\alpha}$ forest data with CMB (Planck+ACT+SPT+WMAP polarization) measurements, and $N_{eff}=2.88{\pm}0.20$ (95% CL) and ${Sigma}m_{\nu}$ < 0.14 eV (95% CL) when we further add baryon acoustic oscillations. Our results tend to favor the normal hierarchy scenario for the masses of the active neutrino species, provide strong evidence for the Cosmic Neutrino Background from $N_{eff}{\approx}3$($N_{eff}=0$ is rejected at more than $14{\sigma}$), and rule out the possibility of a sterile neutrino thermalized with active neutrinos (i.e., $N_{eff}=4$) - or more generally any decoupled relativistic relic with $${\Delta}N_{eff}{\sim_=}1$$ - at a significance of over $5{\sigma}$, the strongest bound to date, implying that there is no need for exotic neutrino physics in the concordance ${\Lambda}CDM$ model.

• 한국전산구조공학회:학술대회논문집
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• 한국전산구조공학회 2008년도 정기 학술대회
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• pp.567-572
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• 2008

This paper's purpose is to improve determining of the critical response of curved bridge to multi-component seismic motion. There are several methods to combine responses by multi-component excitation response, 30%, 40% rules and square-root-of-sum (SRSS). These combination rules determine same value of critical response in straight bridges. However, each method has critical response value of different magnitude in curved bridges. Thus a study about critical response of curved bridges is required. This paper presents comparison critical responses value as each combination rule, 30%, 40% rules and SRSS on curved bridges with the different radiuses of curvature. This study was carried out by response spectrum analysis of OO IC steel box girder bridge using SAP2000. It is concluded as follows: 1) In curved bridges, 30% and 40% rules tend to underestimate the critical response relatively to SRSS. 2) When bridges have smaller radiuses than 100m, difference between SRSS and 30% or 40% rules let run errors up as radiuses of curvature decreased.

• 한국IT서비스학회지
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• 제14권2호
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• pp.69-86
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• 2015

The current contract awarding process regulated by laws and ordinances is analyzed and more reasonable processes are suggested. To this end, the principle of economic analysis is described with emphasis on the cost-effectiveness analysis, and the laws and ordinances regulating the process are thoroughly examined. The current contract awarding rule is based on the weighted sum of effectiveness score and cost score. This may not conform to the framework of economic analysis where effectiveness is supposed to be measured as an output and cost measured as an input. An improvement is attempted to the defense acquisition system and it is recognized that the economic analysis and policy consideration should be performed separately. Concept of statistical testing is introduced to see if the results of the cost effectiveness analyses show the significant difference between the alternatives. It is suggested that the contract awarding process can be improved by performing significance test followed by the aggregation of the two analyses. A minor improvement is also suggested on the application of current rules.

• 전기학회논문지
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• 제57권3호
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• pp.518-526
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• 2008

The fuzzy self-tuning PID controller is a PID controller with a fuzzy logic mechanism for tuning its gains on-line. In this structure, the proportional, integral and derivative gains are tuned on-line with respect to the change of the output of system under control. This paper deals with two types of fuzzy self-tuning PID controllers, rule-based fuzzy PID controller and learning fuzzy PID controller. As a medical application of fuzzy PID controller, the proposed controllers were implemented and evaluated in a laparoscopic surgery robot system. The proposed fuzzy PID structures maintain similar performance as conventional PID controller, and enhance the position tracking performance over wide range of varying input. For precise approximation, the fuzzy PID controller was realized using the linear reasoning method, a type of product-sum-gravity method. The proposed controllers were compared with conventional PID controller without fuzzy gain tuning and was proved to have better performance in the experiment.

• 품질경영학회지
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• 제17권2호
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• pp.17-26
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• 1989

This paper is concerned with forecasting the existing number of errors in the computer software and optimizing the stopping time of the software test based upon the forecasted number of errors. The most commonly used models have assessed software reliability under the assumption that the software failure late is proportional to the current fault content of the software but invariant to time since software faults are independents of others and equally likely to cause a failure during testing. In practice, it has been observed that in many situations, the failure rate decrease. Hence, this paper proposes a mathematical model to describe testing situations where the failure rate of software limearly decreases proportional to testing time. The least square method is used to estimate parameters of the mathematical model. A cost model to optimize the software testing time is also proposed. In this cost mode two cost factors are considered. The first cost is to test execution cost directly proportional to test time and the second cost is the failure cost incurred after delivery of the software to user. The failure cost is assumed to be proportional to the number of errors remained in the software at the test stopping time. The optimal stopping time is determined to minimize the total cost, which is the sum of test execution cast and the failure cost. A numerical example is solved to illustrate the proposed procedure.

• 대한산업공학회지
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• 제36권2호
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• pp.125-137
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• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.