• 한국전기전자재료학회논문지
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• 제20권6호
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• pp.491-495
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• 2007

This paper has demonstrated the electrical properties of SiGe pMOSFETs fabricated on both bulk-Si and PD SOI substrates. Two principal merits, the mobility increase in strained-SiGe channel and the parasitic capacitance reduction of SOI isolation, resulted in improvements in device performance. It was observed that the SiGe PD SOI could alleviate the floating body effect, and consequently DIBL was as low as 10 mV/V. The cut-off frequency of device fabricated on PD SOI substrate was roughly doubled in comparison with SiGe bulk: from 6.7 GHz to 11.3 GHz. These experimental result suggests that the SiGe PD SOI pMOSFET is a promising option to drive CMOS to enhance performance with its increased operation frequency for high speed and low noise applications.

• Journal of Korean Vacuum Science & Technology
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• 제4권1호
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• pp.11-17
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• 2000

The low temperature electron mobilities were investigated in Si/$Si_{1-x}Ge_{x}$ modulation Doped (MOD) quantum well structure with thermally grown oxide. N-type Si/$Si_{1-x}Ge_{x}$ structures were fabricated by a gas source MBE. Thermal oxidation was carried out in a dry $O_2$ atmosphere at $700^{\circ}C$ for 7 hours. Electron mobilities were measured by a Hall effect and a magnetoresistant effect at low temperatures down to 0.4 K. Pronounced Shubnikov-de Haas (SdH) oscillations were observed at a low temperature showing two dimensional electron gases (2 DEG) in a tensile strained Si quantum well. The electron sheet density ($n_{s}$) of 1.5${\times}$$10^{12}$[$cm^{-2}$] and corresponding electron mobility of 14200 [$cm^2$$V^{-1}$$s^{-1}$] were obtained at low temperature of 0.4 K from Si/$Si_{1-x}Ge_{x}$ MOD quantum well structure with thermally grown oxide.

• Journal of Korean Vacuum Science & Technology
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• 제6권2호
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• pp.84-87
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• 2002

The Si$_{1-x}$ Gex/Si surface alloy (x = 0.3, 0.4 and 0.5), which are prepared by solid source MBE and have the SiGe epilayer thickness of 50$\AA$, are annealed with different parameters. The surface structure analyses of the heterostructure samples are made on a triple-axis X-ray diffractometer in grazing incidence X-ray diffraction (GIXRD) geometry. It has been found that with different annealing time (1.5h, 18h, 64h) and annealing temperature (550 $^{\circ}C$, 750 $^{\circ}C$), the SiGe epilayer experienced different strain relaxation process, which was deduced from the GIXRD measurements of the in-plane (220) diffraction peak of Si(001) substrate and the relevant (220) surface diffraction of SiGe epilayer. The results show that the stress relieving and the lateral strain relaxation in the SiGe/Si heterostructure can be promoted by correct annealing, which is very helpful for the preparation of SiGe/Si strained superlattice with fine strain crystallization..

• 한국전기전자재료학회논문지
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• 제17권9호
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• pp.916-923
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• 2004

In this paper, the strained Si$_{0.9}$Ge$_{0.1}$ epitaxial layers grown by a reduced pressure chemical vapor deposition (RPCVD) on Si (100) were characterized by Rutherford backscattering spectrometery (RBS) for the fabrication of an SiGe heterojunction bipolar transistor(HBT). RBS spectra of the ${Si}_0.9{Ge}_0.1$epitaxial layers grown on the Si substrates which were implanted with the phosphorus (P) ion and annealed at a temperature between $850^{\circ}C$ - $1000^{\circ}C$ for 30min were analyzed to investigate the post thermal annealing effect on the grown${Si}_0.9{Ge}_0.1$epitaxial layer quality. Although a damage of the substrates by P ion-implantation might be cause of the increase of RBS yield ratios, but any defects such as dislocation or stacking fault in the grown ${Si}_0.9{Ge}_0.1$ epitaxial layer were not found in transmission electron microscope (TEM) photographs. The post high temperature rapid thermal annealing (RTA) effects on the crystalline quality of the ${Si}_0.9{Ge}_0.1$ epitaxial layers were also analyzed by RBS. The changes in the RBS yield ratios were negligible for RTA a temperature between $900^{\circ}C$ - $1000^{\circ}C$for 20 sec, or $950^{\circ}C$for 20 sec - 60 sec. A SiGe HBT array shows a good Gummel characteristics with post RTA at $950^{\circ}C$ for 20 sec.sec.sec.

• 한국전기전자재료학회논문지
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• 제16권9호
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• pp.765-770
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• 2003

We have developed a low-temperature, and low-pressure radical induced oxidation (RIO) technology, so that high-quality ultrathin silicon dioxide layers have been effectively produced with a high reproducibility, and successfully employed to realize high performace SiGe heterostructure complementary MOSFETs (HCMOS) lot the first time. The obtained oxide layer showed comparable leakage and breakdown properties to conventional furnace gate oxides, and no hysteresis was observed during high-frequency capacitance-voltage characterization. Strained SiGe HCMOS transistors with a 2.5 nm-thick gate oxide layer grown by this method exhibited excellent device properties. These suggest that the present technique is particularly suitable for HCMOS devices requiring a fast and high-precision gate oxidation process with a low thermal budget.

• 한국진공학회지
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• 제3권3호
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• pp.337-340
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• 1994

기판의 크기에 따른 Strained Layer에서의 응력 풀림 현상을 연구하기 위하여 마이크론 이하에 서 50 마이크론의 크기를 가지는 메사 구조를 제작하였다. 제작된 메사 구조위에 성장시킨 GeSi층은 마 이크로 Raman, XPS, I-V와 C-V측정에 의하여 응력의 풀림현상을 관찰하였다. 이 실험을 통하여 메사 구조 위에 성장시킨 GexSi1-x 층에서의 응력풀림이 편평한 기판위에 성장시킨 경우에 비하여 원활하였 다. 이것은 메사 구조의 가장자리에 Strain Dislocation 이 편중되는 것으로 이해될수 있다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.130-130
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• 2011

최근 반도체 메모리 산업의 발전과 동시에 발생되는 문제들을 극복하기 위한 새로운 기술들이 요구되고 있다. DRAM (dynamic random access memory) 의 경우, 소자의 크기가 수십 나노미터 영역으로 줄어들면서, 단채널 효과에 의한 누설전류와 소비전력의 증가 등이 문제가 되고 있다. 하나의 캐패시터와 하나의 트랜지스터로 구성된 기존의 DRAM은, 소자의 집적화가 진행 되어 가면서 정보저장 능력이 감소하는 것을 개선하기 위해, 복잡한 구조의 캐패시터 영역을 요구한다. 이에 반해 하나의 트랜지스터로 구성되어 있는 1T-DRAM의 경우, 캐패시터 영역이 없는 구조적인 이점과, SOI (silicon-on-insulator) 구조의 기판을 사용함으로써 뛰어난 전기적 절연 특성과 기생 정전용량의 감소, 그리고 기존 CMOS (complementary metal oxide semiconductor) 공정과의 호환성이 장점이다. 또한 새로운 물질 혹은 구조를 적용하여, 개선된 전기적 특성을 통해 1T-DRAM의 메모리 특성을 향상 시킬 수 있다. 본 연구에서는, SOI와 SGOI (silicon-germanium-on-insulator) 및 sSOI (strained-si-on-insulator) 기판을 사용한 MOSFET을 통해, strain 효과에 의한 전기적 특성 및 메모리 특성을 평가 하였다. 그 결과 strained-Si층과 relaxed-SiGe층간의 tensile strain에 의한 캐리어 이동도의 증가를 통해, 개선된 전기적 특성 및 메모리 특성을 확인하였다. 또한 채널층의 결함이 적은 sSOI 기판을 사용한 1T-DRAM에서 가장 뛰어난 특성을 보였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.202-202
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• 2010

최근 반도체 소자의 미세화에 따라, 단채널 효과에 의한 누설전류 및 소비전력증가 등이 문제가 되고 있다. DRAM의 경우, 캐패시터 영역의 축소문제가 소자집적화를 방해하는 요소로 작용하고 있다. 1T-DRAM은 기존의 DRAM과 달리 캐패시터 영역을 없애고 상부실리콘의 중성영역에 전하를 저장함으로써 소자집적화에 구조적인 이점을 갖는다. 또한 silicon-on-insulator (SOI) 기판을 이용할 경우, 뛰어난 전기적 절연 특성과 기생 정전용량의 감소, 소자의 저전력화를 실현할 수 있다. 본 연구에서는 silicon-germanium-on-insulator (SGOI) 기판을 이용한 1T-DRAM의 열처리온도에 따른 특성 변화를 평가하였다. 기존의 SOI 기판을 이용한 1T-DRAM과 달리, SGOI 기판을 사용할 경우, strained-Si 층과 relaxed-SiGe 층간의 격자상수 차에 의한 캐리어 이동도의 증가효과를 기대할 수 있다. 하지만 열처리 시, SiGe층의 Ge 확산으로 인해 상부실리콘 및 SiGe 층의 두께를 변화시켜, 소자의 특성에 영향을 줄 수 있다. 열처리는 급속 열처리 공정을 통해 $850^{\circ}C$와 $1000^{\circ}C$로 나누어 30초 동안 N2/O2 분위기에서 진행하였다. 그리고 Programming/Erasing (P/E)에 따라 달라지는 전류의 차를 감지하여 제작된 1T-DRAM의 메모리 특성을 평가하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2004년도 제27회 학술발표회 초록집
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• pp.129-129
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• 2004

• 한국진공학회:학술대회논문집
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• 한국진공학회 1998년도 제14회 학술발표회 논문개요집
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• pp.156-157
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• 1998

It is a diffcult and challenging pproblem to control the growth of eppitaxial films. Heteroeppitaxy is esppecially idfficult because of the lattice mismatch between sub-strate and depposited layers. This mismatch leads usually to a three dimensional(3D) island growth. But the use of surfactants such as As, Sb, and Bi can be beneficial in obtaining high quality heteroeppitaxial films. In this study medium energy ion scattering sppectroscoppy(MEIS) was used in order to reveal the growth mode of Ge on Si(001) and the strain of depposited film without and with dynamically supplied atomic hydrogen at the growth thempperature of 35$0^{\circ}C$. It was ppossible to control the growth mode from layer-by-layer followed by 3D island to layer-by-layer by controlling the hydrogen flux. In the absent of hydro-gen the film grows in the layer-by-layer mode within the critical thickness(about 3ML) and the 3D island formation is followed(Fig1). The 3D island formation is suppressed by introducing hydrogen resulting in layer-by-layer growth beyond the critical thickness(Fig2) We measured angular shift of blocking dipp in order to obtain the structural information on the thin films. In the ppressence of atomic hydrogen the blocking 야 is shifted toward higher scattering angle about 1。. That means the film is distorted tetragonally and strained therefore(Fig4) In other case the shift of blocking dipp at 3ML is almost same as pprevious case. But above the critical thickness the pposition of blocking dipp is similar to that of Si bulk(Fig3). It means the films is relaxed from the first layer. There is 4.2% lattice mismatch between Ge and Si. That mismatch results in about 2。 shift of blocking dipp. We measured about 1。 shift. This fact could be due to the intermixing of Ge and Si. This expperimental results are consistent with Vegard's law which says that the lattice constant of alloys is linear combination of the lattic constants of the ppure materials.