• Title/Summary/Keyword: strained-Si

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Study of Capacitorless 1T-DRAM on Strained-Silicon-On-Insulator (sSOI) Substrate Using Impact Ionization and Gate-Induced-Dran-Leakage (GIDL) Programming

  • Jeong, Seung-Min;Jeong, Hong-Bae;Lee, Yeong-Hui;Jo, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.08a
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    • pp.285-285
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    • 2011
  • 최근 반도체 소자의 미세화에 따라, 단채널 효과에 의한 누설전류 및 소비전력의 증가 등이 문제되고 있다. 대표적인 휘발성 메모리인 dynammic random access memory (DRAM)의 경우, 소자의 집적화가 진행됨에 따라 저장되는 정보의 양을 유지하기 위해 캐패시터영역의 복잡한 공정을 요구하게 된다. 하나의 캐패시터와 하나의 트랜지스터로 이루어진 기존의 DRAM과 달리, single transistor (1T) DRAM은 silicon-on-insulator (SOI) 기술을 기반으로 하여, 하나의 트랜지스터로 DRAM 동작을 구현한다. 이러한 구조적인 이점 이외에도, 우수한 전기적 절연 특성과 기생 정전용량 및 소비 전력의 감소 등의 장점을 가지고 있다. 또한 strained-Si 층을 적용한 strained-Silicon-On-Insulator (sSOI) 기술을 이용하여, 전기적 특성 및 메모리 특성의 향상을 기대 할 수 있다. 본 연구에서는 sSOI 기판위에 1T-DRAM을 구현하였으며, impact ionization과 gate induced-drain-leakage (GIDL) 전류에 의한 메모리 구동 방법을 통해 sSOI 1T-DRAM의 메모리 특성을 평가하였다. 그 결과 strain 효과에 의한 전기적 특성의 향상을 확인하였으며, GIDL 전류를 이용한 메모리 구동 방법을 사용했을 경우 낮은 소비 전력과 개선된 메모리 윈도우를 확인하였다.

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DC and RF Characteristics of $Si_{0.8}Ge_{0.2}$ pMOSFETs: Enhanced Operation Speed and Low 1/f Noise

  • Song, Young-Joo;Shim, Kyu-Hwan;Kang, Jin-Young;Cho, Kyoung-Ik
    • ETRI Journal
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    • v.25 no.3
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    • pp.203-209
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    • 2003
  • This paper reports on our investigation of DC and RF characteristics of p-channel metal oxide semiconductor field effect transistors (pMOSFETs) with a compressively strained $Si_{0.8}Ge_{0.2}$ channel. Because of enhanced hole mobility in the $Si_{0.8}Ge_{0.2}$ buried layer, the $Si_{0.8}Ge_{0.2}$ pMOSFET showed improved DC and RF characteristics. We demonstrate that the 1/f noise in the $Si_{0.8}Ge_{0.2}$ pMOSFET was much lower than that in the all-Si counterpart, regardless of gate-oxide degradation by electrical stress. These results suggest that the $Si_{0.8}Ge_{0.2}$ pMOSFET is suitable for RF applications that require high speed and low 1/f noise.

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Strain Relief of$ Ge_xSi_{1-x}$ (100) Mesa Structure (Si(100) 메사 구조위에 성장시킨$ Ge_xSi_{1-x}$ 층에서의 응력 풀림)

  • Kang, Yoon-Ho;Kuk, Young
    • Journal of the Korean Vacuum Society
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    • v.3 no.3
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    • pp.337-340
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    • 1994
  • 기판의 크기에 따른 Strained Layer에서의 응력 풀림 현상을 연구하기 위하여 마이크론 이하에 서 50 마이크론의 크기를 가지는 메사 구조를 제작하였다. 제작된 메사 구조위에 성장시킨 GeSi층은 마 이크로 Raman, XPS, I-V와 C-V측정에 의하여 응력의 풀림현상을 관찰하였다. 이 실험을 통하여 메사 구조 위에 성장시킨 GexSi1-x 층에서의 응력풀림이 편평한 기판위에 성장시킨 경우에 비하여 원활하였 다. 이것은 메사 구조의 가장자리에 Strain Dislocation 이 편중되는 것으로 이해될수 있다.

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Real-time Observation of Evolution Dynamics of Ge Nanostructures on Si Surfaces by Photoelectron Emission Microscopy (자외선 광여기 전자현미경을 이용한 Si 표면 위에 Ge 나노구조의 성장 동역학에 관한 실시간 연구)

  • Cho, W.S.;Yang, W.C.;Himmerlich, M.;Nemanich, R.J.
    • Journal of the Korean Vacuum Society
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    • v.16 no.2
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    • pp.145-152
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    • 2007
  • The evolution dynamics of nanoscale Ge islands on both Si (001) and (113) surfaces is explored using ultraviolet photoelectron emission microscopy (UV-PEEM). Real-time monitoring of the in-situ growth of the Ge island structures can allow us to study the variation of the size, the shape and the density of the nanostructures. For Ge depositions greater than ${\sim}4$ monolayer (ML) with a growth rate of ${\sim}0.4\;ML/min$ at temperatures of $450-550^{\circ}C$, we observed island nucleation on both surfaces indicating the transition from strained layer to island structure. During continuous deposition the circular islands grew larger via ripening processes. AFM measurements showed that the islands grown on Si (001) were dome-shaped while the islands on Si (113) were multiple-side faceted with flat tops of (113)-orientation. In contrast, for Ge deposition with a lower growth rate of ${\sim}0.15\;ML/min$ on Si(113), we observed the shape transition from circular into elongated island structures. The elongated islands grew longer along the [$33\bar{2}$] during continuous Ge deposition. The shape evolution of the islands is discussed in terms of strain relaxation and kinetic effects.

Grazing Incidence X-ray Diffraction (GIXRD) Studies of the Structure of Si$_{1-x}Ge_x$/Si Surface Alloy

  • Shi, Y.;Zhao, R.;Jiang, C.Z.;Fan, X.J.
    • Journal of Korean Vacuum Science & Technology
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    • v.6 no.2
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    • pp.84-87
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    • 2002
  • The Si$_{1-x}$ Gex/Si surface alloy (x = 0.3, 0.4 and 0.5), which are prepared by solid source MBE and have the SiGe epilayer thickness of 50$\AA$, are annealed with different parameters. The surface structure analyses of the heterostructure samples are made on a triple-axis X-ray diffractometer in grazing incidence X-ray diffraction (GIXRD) geometry. It has been found that with different annealing time (1.5h, 18h, 64h) and annealing temperature (550 $^{\circ}C$, 750 $^{\circ}C$), the SiGe epilayer experienced different strain relaxation process, which was deduced from the GIXRD measurements of the in-plane (220) diffraction peak of Si(001) substrate and the relevant (220) surface diffraction of SiGe epilayer. The results show that the stress relieving and the lateral strain relaxation in the SiGe/Si heterostructure can be promoted by correct annealing, which is very helpful for the preparation of SiGe/Si strained superlattice with fine strain crystallization..

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High Quality Ultrathin Gate Oxides Grown by Low-Temperature Radical Induced Oxidation for High Performance SiGe Heterostructure CMOS Applications (저온 래디컬 산화법에 의한 고품질 초박막 게이트 산화막의 성장과 이를 이용한 고성능 실리콘-게르마늄 이종구조 CMOS의 제작)

  • 송영주;김상훈;이내응;강진영;심규환
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.9
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    • pp.765-770
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    • 2003
  • We have developed a low-temperature, and low-pressure radical induced oxidation (RIO) technology, so that high-quality ultrathin silicon dioxide layers have been effectively produced with a high reproducibility, and successfully employed to realize high performace SiGe heterostructure complementary MOSFETs (HCMOS) lot the first time. The obtained oxide layer showed comparable leakage and breakdown properties to conventional furnace gate oxides, and no hysteresis was observed during high-frequency capacitance-voltage characterization. Strained SiGe HCMOS transistors with a 2.5 nm-thick gate oxide layer grown by this method exhibited excellent device properties. These suggest that the present technique is particularly suitable for HCMOS devices requiring a fast and high-precision gate oxidation process with a low thermal budget.

Comparison of Electrical Characteristics of SiGe pMOSFETs Formed on Bulk-Si and PD-SOI (Bulk-Si와 PD-SOI에 형성된 SiGe p-MOSFET의 전기적 특성의 비교)

  • Choi, Sang-Sik;Choi, A-Ram;Kim, Jae-Yeon;Yang, Jeon-Wook;Han, Tae-Hyun;Cho, Deok-Ho;Hwang, Yong-Woo;Shim, Kyu-Hwan
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.20 no.6
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    • pp.491-495
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    • 2007
  • This paper has demonstrated the electrical properties of SiGe pMOSFETs fabricated on both bulk-Si and PD SOI substrates. Two principal merits, the mobility increase in strained-SiGe channel and the parasitic capacitance reduction of SOI isolation, resulted in improvements in device performance. It was observed that the SiGe PD SOI could alleviate the floating body effect, and consequently DIBL was as low as 10 mV/V. The cut-off frequency of device fabricated on PD SOI substrate was roughly doubled in comparison with SiGe bulk: from 6.7 GHz to 11.3 GHz. These experimental result suggests that the SiGe PD SOI pMOSFET is a promising option to drive CMOS to enhance performance with its increased operation frequency for high speed and low noise applications.

Study on Structural properties of As Ion -Implanted Si (As이온이 주입된 Si의 구조적 특성 연구)

  • 믄영희;배인호;김말문;한병국;김창수;홍승수;신용현;정광화
    • Journal of the Korean Vacuum Society
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    • v.5 no.3
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    • pp.218-222
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    • 1996
  • STrained layers and strain depth profile of high dose As ion implanted (100) si wafer annealed at various temperatures have been investigated by means of X-ray double crystal diffractometry (X-ray DCD). The results obtained by x-ray rocking curve analysis showed a defect layer at the original amorphous /crystalline interface of 1400$\AA$ depth. In addition arsenic ion concentrtion profiles and defect distributions in depth were obtained by the SIMS and TRIM -code simulation . the positive strain depth profile determined from the rocking curve analysis were only presented under 0.14 $\mu$m from the surface for samples ananelaed at $600^{\circ}C$. The results was shown that the thickness of amprphous layer is 0.14 $\mu$m indirectry, and it was good agreement with the TRIM -Code simulation. Additionally, it could be thought that the positive strain have been affected residual intersitial atoms under the amorphous/crystalline interface formed by ion implantation.

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Surface and Interface Analysis with Medium Energy Ion Scattering Spectroscoppy

  • Moon, Dae-Wom
    • Proceedings of the Korean Vacuum Society Conference
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    • 1998.02a
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    • pp.129-129
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    • 1998
  • Most of the surface/interface analysis tools have limited depth profiling c capability in terms of the profiling range and the depth resolution. However, M MEIS can profile the surface and subsurface composition and structure q quantitatively and non-destructively with atomic layer depth resolution. I In this presentation, the MEIS system developed at KRISS will be briefly d described with an introduction on the principle of MEIS. Recent MEIS r results on the surface and interface composition and structural change due to i ion bombardment will be presented for preferential sputtering of T:없Os and d damage depth profiles of SHooD, Pt(l11), and Cu(l1D due to Ar+ ion b bombardment. Direct observation of strained Si lattices and its distribution i in the SHool)-SiCh interface and the initial stage of Co growth on Pt(l11) w will be reported. H surfactant effects on epitaxial growth of Ge on Si(ooD w will be discussed with STM results from SND.

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