• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.29.1-29.1
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• 2009

반도체 공정에서의 금속 배선 공정은 매우 중요한 공정 중 하나이다. 기존에 사용되던 알루미늄이 한계에 다다르면서, 대체 재료로 사용되고있는 구리는 낮은 비저항, 높은 열전도도, 우수한 electromigration(EM)저항특성 등을 바탕으로 차세대 nano-scale집적회로의 interconnect application에 적합한 금속재료로서 각광받고 있다. Electroplating을 위한 구리 seed layer CVD 공정은 타 공정에 비해 step coverage가 우수한 막을 증착할 수 있어 고집적 소자의 구현이 가능하다. 본 연구에 이용된 2가 전구체 Cu(dmamb)2는 높은 증기압과 높은 활성화 에너지를 가짐으로서 열적안정성 및 보관안정성이 우수하며, 플루오르를 함유하지 않아 친환경적이다. 구리 증착 전 기판에 plasma 처리를 하면 표면 morphology가 변함에 따라 표면 에너지가 변화하고, 이는 구리의 2차원 성장에 유리하게 작용할 것으로 여겨진다. Plasma의 조건변화에 따른 기판의 morphology 변화 및 성막된 구리의 특성 변화를 분석하였다.

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.28-31
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• 2013

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.

• MALSORI
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• no.56
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• pp.147-158
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• 2005

In this paper, we are focused to develop the simplified speaker verification algorithm without background speaker models, which will be adopted in the portable speaker verification system equipped in portable terminals such as mobile phone and PMP. According to the tolerance interval analysis, the population of someone's speaker model can be represented by a suitable number of selected independent samples of speaker model. So we can make the representative speaker model and threshold under the specified confidence level and coverage. Using proposed algorithm with the number of samples is 40, the experiments show that the false rejection rate is $3.0\%$ and the false acceptance rate $4.3\%$, worth comparing to conventional method's results, $5.4\%\;and\;5.5\%$, respectively. Next step of research will be on the suitable adaptation methods to overcome speech variation problems due to aging effect and operating environments.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.118-128
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• 1995

Copper(l) hexafluoroacetonate trimethylvinylsilane [Cu(hafac)(TMVS)]를 precursor로 사용하여 증착온도 $160~330^{\circ}C$ 범위에서 TiN 모재 위에 낮은 전기비저항값(~2 $\mu$$\Omega$.cm)을 갖는 CVD Cu 박막을 제조하였고, 증착온도에 따른 Cu 박막의 특성을 조사하여 증착온도가 Cu 박막의 미세구조와 전기비저항에 미치는 영향을 고찰하였다. Cu 증착의 활성화에너지는 표면반응제한지역(surface-reaction-limited region)에서 10.8 kcal/mol 이었다. 표면반응에 의해 증착속도가 결정되는 증착온도 $200^{\circ}C$ 이하에서 증착된 Cu 박막은 낮은 비저항값을 갖는 치밀한 박막이었고 step coverage 또한 우수하였다. 이에 반해 물질전달이 증착속도를 결정하는 증착온도 $200^{\circ}C$이상에서 증착된 Cu 박막은 연결상태가 불량한 구형의 결정립들로 이루어져 있어서 높은 비저항값과 거친 표면형상을 나타내었다. 이와 함께 증착온도에 따른 Cu 박막의 결정립 크기, 배향성 등도 조사하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.98-106
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• 1996

A thin film of aluminum for ultra large scale integrated circuits metalization has been deposited on TiN and SiO$_{2}$ substrates by plasma assisted chemical vapor deposition using DMEAA (dimenthylethylamine alane) as a precursor. The effects of plasma on surface topology and growth characteristics were investigated. Thermal CVD Al could not be got continuous films on insulating subsrate such as SiO$_{2}$. However, it was found that Al films could be deposited on SiO$_{2}$ substate without any pretreatments by the hydrogen plasma for pyrolysis of DMEAA. Compared to the thermal CVD, PACVD films showed much better reflectance and resistance on TiN and SiO$_{2}$ substrate. We obtained mirror-like PACVD Al film of 90% reflectance and resistance on TiN and SiO$_{2}$ substrates. We obtained mirror-like PACVD Al film of 90% reflectance on TiN substrate. Excellent conformal step coverage was obtained on submicron contact holes ;by the PACVD blanket deposition.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.9-12
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• 2008

For the large-sized and post-ultra definition TFT-LCD, improved drivability is prerequisite not only for the integration of driving circuit on glass but also for the chargeability of each pixel. In order to meet required drivability, currently adopted process architecture and materials are modified for the RC delay reduction, including the drastic increase of gate bus thickness and its related solution for step coverage. We present new process architecture and material selection for the next generation TFT-LCD devices.

• Journal of the Korean Ceramic Society
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• v.28 no.7
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• pp.517-524
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• 1991

The CVD process of BPSG (BoroPhosphoSilicate Glass) and its thin film properties were studied. B2H6, PH3, SiH4 and O2 gases were reacted in a AP (Atmospheric Pressure) CVD system in the temperature range of 300℃ and 460℃. The interaction of B2H6 and PH3 was studied from the deposition rate and dopant incorporation change point of view. The dependency of BPSG step coverage on the temperature was changed with different O2/(B2H6+PH3+SiH4) ratio. Finally, the boundary which distinguishes the stable BPSG's from the ones that react with Di (Deionized) water or cleaning chemicals such as H2SO4, HCl, H2O2, NH4OH etc could be defined.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.940-943
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• 2005

The characteristics of a-Si:H TFTs with silicon oxide as passivation layer were reported. It was studied that the insulating characteristics and step coverage characteristics of low temperature silicon oxide before applying to a-Si:H TFT fabrications. With the optimum deposition conditions considering electrical and deposition characteristics, low temperature silicon oxide was applied to a-Si:H TFTs. The changes in characteristics of a-Si:H TFTs were analyzed after replacing silicon nitride passivation layer with low temperature silicon oxide layer. This low temperature silicon oxide can be adapted to high resolution a-Si:H TFT LCD panels.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.185-188
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• 2001

In this study, $Al_2$O$_3$films have been deposited with Atomic Layer Deposition(ALD) for gate insulator for MPTMA and $H_2O$ at low temperature below 40$0^{\circ}C$ . Conventional methods of $Al_2$O$_3$thin film deposition have suffered from the poor step coverage due to reduction of device dimension and increasing contact/via hole aspect ratio. ALD is a self-limiting growth process with controlled surface reaction where the growth rate is only dependent on the number of growth cycle and the lattice parameter of materials. ALD growth process has many advantages including accurate thickness control, large area and large batch capability, good uniformity, and pinholes freeness.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.41-41
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• 2010

반도체 소자의 선폭이 감소함에 따른 금속배선의 저항이 증가하면서 반도체 배선물질을 copper로 대체하려는 연구가 진행되고 있다. 그러나 copper를 금속배선에 사용하게 되면 대기 상에서 노출 시 쉽게 산화가 일어나며 형성된 산화물의 미세조직이 치밀하지 못하여 계속적인 산화가 진행되고, 후속 열처리 공정 시 copper가 유전체로 확산되어 소자의 정상적인 작동을 방해하게 되는 문제점을 가지고 있다. 이러한 문제점을 해결하기 위해서 copper의 확산 및 산화를 방지하는 물질로 cobalt가 각광받고 있다. Cobalt는 낮은 저항과 열적 안정성이 우수하여 copper와의 연동에 문제가 없으며, 소자의 작동에도 영향을 미치지 않는다. Cobalt 박막의 적용을 위해 patterning 단계를 줄일 수 있는 선택적 증착공정의 개발도 요구되고 있다. 본 연구에서는 우수한 층덮힘(step coverage)과 양질의 박막을 증착할 수 있는 MOCVD 공정을 이용하였고, cobalt 전구체로서 $Co(hfac)_2$ (hfac: hexafluoroacethylacetonate) 전구체와 $Co_2$ (CO)8 (CO: carbonyl) 전구체를 사용하였다. 각각의 전구체에 따라 선택적 증착이 가능한 공정조건을 찾기 위한 연구를 진행하였다.