• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.957-961
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• 2004

In order to realize high performance thin film transistor (TFT) on plastic substrate, Si film was deposited on plastic substrate at 170$^{\circ}C$ by using inductivity coupled plasma chemical vapor deposition (ICPCVD). Hydrogen concentration in as-deposited Si film was 3.8% which is much lower than that in film prepared by using conventional plasma enhanced chemical vapor deposition (PECVD). Si film was deposited as micro crystalline phase rather than amorphous phase even at 170$^{\circ}C$ because of high density plasma. By step-by-step Excimer laser annealing, dehydrogenation and recrystallization of Si film were carried out simultaneously. With step-by-step annealing and optimization of underlayer structure, it has succeeded to achieve large grain size of 300nm by using ICPCVD. Base on these results, poly-Si TFT was fabricated on plastic substrate successfully, and it is sufficient to drive pixels of OLEDs, as well as LCDs.

• Journal of the Korean Vacuum Society
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• v.2 no.2
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• pp.161-165
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• 1993

The geometrical and electronic structure of epitaxially grown Ge on Si(100) and Si(111) surfaces has been studied by scanning tunneling microscopy. Since Ge atoms could be distinguished from Si atoms by scanning tunneling spectroscopy and voltage dependent STM images, the growth mode of the added layer could be studied. On the (100) surface with a (2${\times}$1) reconstruction, Ge overlayer grow preferentially on the B type step edges at 720K. On the (111) surface, Ge overlayer also grow on the step edges with (7${\times}$7) and (5${\times}$5) structure depending on their coverage and annealing temperature.

• Journal of the Korean institute of surface engineering
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• v.33 no.2
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.

• Journal of Welding and Joining
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• v.17 no.1
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• pp.133-144
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• 1999

To fine seam annealer capacity of through thickness seam annealing in terms of through thickness microstructure change with increased toughness and elongation leaving heat trace on it, high strength steel pipes of ERW with different thickness were tested in different seam annealing temperature measured on the outer surface of pipes. Annealing temperature and microstructure of the weld seam were changed through applied seam annealing condition. Toughness and tensile test with hardness and microstructure analysis were done on the annealed weld seam to fine its characteristics as a primary step and annealing characteristics according to different seam annealing condition. Through a study of annealed ERW weld seam characteristics and seam annealing technology, amount of electric power should apply in decreased manner to arranged inductors of annealer in the order of 1st, 2nd, 3rd, so on for proper seam annealing. For example of 15.4mm thick and 610mm outside diameter pipe, applied power for proper seam annealing is 600 -650kw at 1st inductor, 450 - 500kw at 2nd inductor, 200-250 kw at 3rd inductor of annealer during 10 - 12M/minute moving speed of pipe. Also, the penetration depth of heat trace along the thickness direction of weld during seam annealing can be estimated through the equation 17mm/kv$\times$voltage(kv) with the microstructure and hardness analysis of thick weld seam as well as study of seam annealing and comparison of cooling condition to CCT diagram of low carbon high strength steel. From this result, the difference between the technological applicability of full annealing condition based on phase diagram and full penetration of heat trace based on CCT diagram along the thickness of weld seam is discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.725-728
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• 2000

Ferroelectric thin film capacitors with high dielectric constant are important for the application of memory devices. In this work, We have systematically investigated the variation of grain sizes depending on the process condition of two-step process. Both in-situ annealing and ex-annealing have been compared depending on the annealing time. C-V measurement, ferroelectric properties, leakage current, XRD and SEM were performed to investigate the electircal properties and microstructural properties of Pb(La, Ti)O$_3$ films.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.1
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• pp.87-92
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• 2002

Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a stochastic evolution algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.7
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• pp.708-712
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• 2004

Shallow $p^+-n$ junctions were formed by ion implantation and dual-step annealing processes. The dopant implantation was performed into the crystalline substrates using BF$_2$ ions. The annealing was performed with a rapid thermal processor and a furnace. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of junction depth and sheet resistance. A new simulator is designed to model boron diffusion in silicon. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. Using initial conditions and boundary conditions, coupled diffusion equations are solved successfully. The simulator reproduced experimental data successfully.

• Journal of Korea Society of Digital Industry and Information Management
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• v.17 no.2
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• pp.13-20
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• 2021

Placement is a very important step in the VLSI physical design process. It is the problem of placing circuit modules to optimize the circuit performance and reliability of the circuit. It is used at the layout level to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. The most popular algorithms for circuit placement include the cluster growth, simulated annealing, integer linear programming and genetic algorithm. In this paper we propose a adapted genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing and genetic algorithm by analyzing the results of each implementation. As a result, it was found that the adaptive genetic algorithm approaches the optimal solution more effectively than the simulated annealing and genetic algorithm.

• Journal of Ceramic Processing Research
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• v.13 no.spc1
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• pp.59-63
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• 2012

Ga2O3-core/CdO-shell nanowires were synthesized by a two step process comprising thermal evaporation of GaN powders and sputter-deposition of CdO. Transmission electron microscopy (TEM) and X-ray diffraction (XRD) analyses revealed that the cores and the shells of the annealed coaxial nanowires were single crystal of monoclinic Ga2O3 and FCC CdO, respectively. As-synthesized Ga2O3 nanowires showed a broad emission band at approximately 460 nm in the blue region. The blue emission intensity of the Ga2O3 nanowires was slightly decreased by CdO coating, but it was significantly increased by subsequent thermal annealing in a reducing atmosphere. The major emission peak was also shifted from ~500 nm by annealing in a reducing atmosphere, which is attributed to the increases in the Cd interstitial and O vacancy concentrations in the cores.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.351-356
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• 1995

A optical switch which on the LiNbO$_3$substrate is fabricated by using proton exchange method and self-alignet method. The annealing at 400[$^{\circ}C$] was carried out to control waveguide width and depth. A self-aligned method, which doesn\`t need the additional mask precesses, was applied to simplify the fabrication processes and to maximize efficiency of electric field application. The depths of the two annealed optical waveguides, which were measured by using ${\alpha}$-step, ware 1.435[K${\AA}$] and 1,380[K${\AA}$]. Using ${\alpha}$-step facility, we examined that the width of waveguides is increased from 5[$\mu\textrm{m}$] to 6.45[$\mu\textrm{m}$] and 6.3[$\mu\textrm{m}$] due to the annealing effects. The process of proton exchange was done at 400[$^{\circ}C$] for 60[min] and annealing process was done at 400[$^{\circ}C$] for 60[min]. The high speed optical modulator has very good figures of merits: the measured voltage of the input waveguide power is 3.5[V], the voltage of the coupling waveguide power is 3.9[mV], and -29.5[dB] crosstalk and 8[V] switching voltage were achieved.