• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.371-375
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• 2005

In this paper, the resonance characteristics of ZnO-based FBAR devices are compared. Several FBAR device samples were fabricated by using three different annealing methods while one sample remained non-annealed as a reference for comparison. Resonance characteristics could be significantly improved by both Bragg reflector-annealing and/or post-annealing steps. Especially, the use of two-step annealings resulted in most desirable resonance characteristic improvement compared with the Bragg reflector-annealing or post-annealing step alone.

• 한국진공학회지
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• 제4권S2호
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• pp.69-74
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• 1995

The effects of TCA incorporation during annealing process on the SIMOX quality is studied. Silicon wafers are implanted with heavy dose of oxygen ions, and are annealed at $1300^{\circ}C$ for 4 hours. The annealing process is splitted into three conditions due to some differences of low temperature preliminary annealing step which are without pre-annealing step. The specimens are analyzed by several methods, such as AES, XTEM, and TRXFA. TCA incorporation during pre-annealing step is effective in dislocation density reduction and heavy metal content reduction.

• KIEE International Transactions on Electrophysics and Applications
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• 제3C권2호
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• pp.43-47
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• 2003

Lead zirconate titanate (PZT) thin films were fabricated by the pulsed laser ablation deposition (PLAD) method onto Pt/Ti/SiO$_2$/Si substrates. Crystalline phases as well as preferred orientations in PZT films were investigated by X-ray diffraction analysis (XRD). The well-crystallized perovskite phase and the (101) preferred orientation were obtained by two-step annealing at the conditions of $650^{\circ}C$, 1 hour. It was found that the temperature for the pulsed laser ablated PZT films annealed via a two-step annealing process can be reduced 20$0^{\circ}C$ compared to that of the conventional three-step annealing temperature profile for enhancing the transformation of the perovskite phase. The remanent polarization and the coercive field of this film were about 20 $\mu$C/$\textrm{cm}^2$ and 46 kV/cm, while the dielectric constant and loss values measured at 1 KHz were approximately 860 and 0.04, respectively. The interesting phenomena of this film, such as vertical shift in hysteresis curve, are also discussed.

• Transactions on Electrical and Electronic Materials
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• 제17권3호
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• pp.134-138
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• 2016

The fullerene solar cells are becoming a feasible choice due to the advanced developments in donor materials and improved fabrication techniques of devices. Recently, sufficient optimization and improvements in the processing techniques like incorporation of solvent vapor annealing (SVA) with additives in solvents has become a major cause of prominent improvements in the performance of organic solar cell-based devices . On the other hand, the challenge of reduced open circuit voltage (V_oc) remains. This study presents an approach for significant performance improvement of overall device based on organic small molecular solar cells (SMSCs) by following a two step technique that comprises thermal annealing (TA) and SVA (abbreviated as SVA+TA). In case of exclusive use of SVA, reduction in V_oc can be eliminated in an effective way. The characteristics of charge carriers can be determined by the measurement of transient photo-voltage (TPV) and transient photo-current (TPC) that determines the scope for improvement in the performance of device by two step annealing. The recovery of reduced V_oc is linked with the necessary change in the dynamics of charge that lead to increased overall performance of device. Moreover, SVA and TA complement each other; therefore, two step annealing technique is an appropriate way to simultaneously improve the parameters such as V_oc, fill factor (FF), short circuit current density (J_sc) and PCE of small molecular solar cells.

• Current Photovoltaic Research
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• 제7권1호
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• pp.1-8
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• 2019

The $Cu(In,Ga)Se_2$ (CIGS) thin film obtained by two-step process (metal deposition and Se annealing) has a rough surface morphology and many voids at the CIGS/Mo interface. To solve the problem a precursor that contains Se was employer by depositing a (In,Se)/(Cu,Ga) stacked layer. We devised a two-step annealing (vacuum pre-annealing and Se annealing) for the precursor because direct annealing of the precursor in Se environment resulted in the small grains with unwanted demarcation between stacked layers. After vacuum pre-annealing up to $500^{\circ}C$ the CIGS film consisted of CIGS phase and secondary phases including $In_4Se_3$, InSe, and $Cu_9(In,Ga)_4$. The secondary phases were completely converted to CIGS phase by a subsequent Se annealing. A void-free CIGS/Mo interface was obtained by the two-step annealing process. Especially, the CIGS film prepared by vacuum annealing $450^{\circ}C$ and subsequent Se annealing $550^{\circ}C$ showed a densely-packed grains with smooth surface, well-aligned bamboo grains on the top of the film, little voids in the film, and also little voids at the CIGS/Mo interface. The smooth surface enhanced the cell performance due to the increase of shunt resistance.

• 동력기계공학회지
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• 제2권3호
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• pp.60-67
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• 1998

Edge detection is the first step and very important step in image analysis. We cast edge detection as a problem in cost minimization. This is achieved by the formulation of a cost function that evaluates the quality of edge configurations. The cost function can be used as a basis for comparing the performances of different detectors. This cost function is made of desirable characteristics of edges such as thickness, continuity, length, region dissimilarity. And we use a simulated annealing algorithm for minimum of cost function. Simulated annealing are a class of adaptive search techniques that have been intensively studied in recent years. We present five strategies for generating candidate states. Experimental results(building image and test image) which verify the usefulness of our simulated annealing approach to edge detection are better than other operator.

• 한국전기전자재료학회논문지
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• 제24권7호
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• pp.525-531
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• 2011

In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.185-188
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• 1997

The influence of slow cooling and annealing time in $O_2$ during melting and growth step in MPMG process on J$_{c}$ was investigated. Through the measurement of J$_{c}$ SEM and XRD, it can be observed that the critical characteristics were related with the slow cooling time and annealing time in 02 for melting and growth step of MPMG process. The distribution of critical current density with slow cooling time was the porabolic form and the value of J. was the highest at the 40 hour slow cooling time. And also, the value of J$_{c}$, along the annealing time in $O_2$ in the case of the slow cooling time 40 hour was inclined to increase with annealing time. Consequently, it can be suggested that proper slow cooling titre and annealing time along slow cooling in MPMG process be important to improve the critical characteristics.stics.

• Journal of Korean Vacuum Science & Technology
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• 제6권2호
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• pp.79-83
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• 2002

As Ag does not form my silicide on Si surfaces, Ag wire is a candidate for self-assembled nanowire on the reconstructed and single-domain Si(5 5 12)-2 $\times$ 1. In the present study, various Ag coverages and post-annealing temperatures had been tested to fabricate a Ag nanowire with high aspect ratio. When Ag coverage was less than 0.03 ML and the post-annealing temperature was 500(C, Ag atoms preferentially adsorbed on the tetramer sites resulting in Ag wires with an inter-row spacing of ~5 nm. However, its aspect ratio is relatively small and its height is also not even. On the other hand, the Ag-posited surface completely loses its reconstruction even with the same annealing at 500 $\^{C}$ if the initial coverage exceeds 0.05 ML. But the additional subsequent annealing at 700$\^{C}$ and slow-cooling process recovers the well-ordered Ag chain with relatively high aspect ratio on the same tetramer sites. It can be understood that, in the double step annealing process, the lower temperature annealing is required for cohesion of adsorbed Ag atoms and the higher temperature annealing is for providing Ag atoms to the tetramer sites.

• Transactions on Electrical and Electronic Materials
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• 제9권4호
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• pp.137-142
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• 2008

The parasitic resistance is studied to silicon/metal contact junction for improving device performance and to lower contact/serial resistance silicide in natural sequence. In this paper constructs the stepwise Ni silicide process for parasitic resistance reduction for silicon/metal contact junction. We have investigated multi-step Ni silicide on SiGe substrate with stepwise annealing method as an alternative to compose more thermally reliable Ni silicide layer. Stepwise annealing for silicide formation is exposed to heating environment with $5^{\circ}C/sec$ for 10 seconds and a dwelling for both 10 and 30 seconds, and ramping-up and the dwelling was repeated until the final annealing temperature of $700\;^{\circ}C$ is achieved. Finally a direct comparison for single step and stepwise annealing process is obtained for 20 nm nickel silicide through stepwise annealing is $5.64\;{\Omega}/square$ at $600\;^{\circ}C$, and it is 42 % lower than that of as nickel sputtered. The proposed stepwise annealing for Ni silicidation can provide the least amount of NiSi at the interface of nickel silicide and silicon, and it provides lower resistance, higher thermal-stability, and superior morphology than other thermal treatment.