• 한국철도학회:학술대회논문집
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• 한국철도학회 1999년도 춘계학술대회 논문집
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• pp.238-247
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• 1999

A study on the static type simulator will include an instructor's station, two cabs for ISA with visual and sound system, and realistic and accurate model of the trains operation. The simulator is easy to extend and maintenance using structured the S/W. The training of new drives requires that the environment of the cab, controls placement, etc. must highly realistic so that driver can readily transfer his training experience to the real world. The simulator detailed software model and extensive scenario design capability allows both for a wide variety of scenarios and accurately modeled response covering most aspects of brakes, rules, and faults.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 A
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• pp.193-195
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• 2003

This paper presents an approach to estimate the power transmission line parameter by phasor measurement units(PMUs), which are synchronized to 1 pps signal of GPS. Existing approaches to estimate power transmission line parameter, are mainly off-line ones, based on faults or switching events on other neighboring lines. In this paper, to obtain static and dynamic properties of power transmission line parameter in service, the prototype of pmu-based Transmission Line Parameter Monitoring System (TLPMS) is proposed. Also, an technique to estimate parameters of transmission line described as 2-port network model and the soundness of estimated parameters are addressed.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2006년도 추계학술대회 논문집
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• pp.1468-1476
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• 2006

The goal of this thesis is to support safety and reliability characteristics of software intensive critical systems. The verification method developed is innovative from current state of the art in what concerns the verification viewpoint adopted: focusing on software faults, and not, like many other approaches purely on fulfilling functional requirements. As a first step and based on a number of well defined criteria a comparison was made of available literature in the area of static non formal non probabilistic software fault removal techniques. But, None of the techniques evaluated fulfilled all criteria set in isolation. Therefore a new technique was developed based on a combination of two existing techniques: the FMEA and FTA. These two techniques complement each other very well. It is possible to integrate both techniques with commonly used techniques at system level. The resulting new technique can be shown to combine nearly all aspects of existing fault removal techniques.

• Journal of Electrical Engineering and information Science
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• 제1권1호
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• pp.118-128
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• 1996

In safety critical hard real-time systems, a timing fault may yield catastrophic results. In order to eliminate the timing faults from the fast responsive real-time control systems, it is necessary to schedule a code based on high precision timing analysis. Further, the schedulability enhancement by having multiple processors is of wide spread interest. However, although an instruction level parallel processing is quite effective to improve the schedulability of such a system, none of the real-time applications employ instruction level parallel scheduling techniques because most of the real-time scheduling models have not been designed for fine-grain execution. In this paper, we present a timing constraint model specifying high precision timing constraints, and a practical approach for constructing static schedules for a VLIW execution model. The new model and analysis can guarantee timing accuracy to within a single machine clock cycle.

• Journal of Power Electronics
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• 제18권2호
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• pp.627-639
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• 2018

The fact that the reliability of IGBTs has become a more and more significant aspect of power converters has resulted in an increase in the research on the open circuit (OC) fault location of IGBTs. When an OC fault occurs, a zero-current phenomena exists and frequently appears, which can be found in a lot of the existing literature. In fact, fault variables have a very high correlation with the zero-current interval. In some cases, zero-current interval actually decides the most significant fault feature. However, very few of the previous studies really explain or prove the zero-current phenomena of the fault current. In this paper, the zero-current phenomena is explained and verified through mathematical derivation, based on two-level and three-level NPC static var generators (SVGs). Mathematical models of single OC fault are deduced and it is concluded that a zero-current interval with a certain length follows the OC faults for both two-level and NPC three-level SVGs. Both inductive and capacitive reactive power situations are considered. The unbalanced load situation is discussed. In addition, simulation and experimental results are presented to verify the correctness of the theoretical analysis.

• 한국정보과학회논문지:시스템및이론
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• 제26권10호
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• pp.1264-1274
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• 1999

본 논문에서는 분산된 클록들을 주기적으로 동기화 시키는 분산 실시간 시스템에서 시간적 제약을 만족시키기 위한 정적/동적 시간 제약(timing constraint) 변환 기법을 제안한다. 전형적인 이산클록동기화(discrete clock synchronization) 알고리즘은 클록의 값을 순간적으로 조정하여 클록의 시간이 불연속적으로 진행한다. 이러한 시간상의 불연속성은 시간적 이벤트를 잃어버리거나 다시 발생시키는 오류를 범하게 한다.클록 시간의 불연속성을 피하기 위해 일반적으로 연속클록동기화(continuous clock synchronization) 기법이 제안되고 있지만 소프트웨어적으로 구현되면 많은 오버헤드를 유발시키는 문제점이 있다. 본 논문에서는 시간적 제약을 동적으로 변환시키는 DCT (Dynamic Constraint Transformation) 기법을 제안하였으며, 이를 통해 기존의 이산클록동기화 알고리즘을 수정하지 않고서도 클록 시간의 불연속성에 의한 문제점들을 해결할 수 있도록 하였다. 아울러 DCT에 의해 이산클록동기화 하에서 생성된 태스크 스케쥴이 연속클록동기화에 의해 생성된 스케쥴과 동일함을 증명하여 DCT의 동작이 이론적으로 정확함을 증명하였다.또한 분산 실시간 시스템에서 지역 클록(local clock)이 기준 클록과 완벽하게 일치하지 않아서 발생하는 스케쥴링상의 문제점을 다루었다. 이를 위해 먼저 두 가지의 스케쥴링 가능성, 지역적 스케쥴링 가능성(local schedulability)과 전역적 스케쥴링 가능성(global schedulability)을 정의하고, 이를 위해 시간적 제약을 정적으로 변환시키는 SCT (Static Constraint Transformation) 기법을 제안하였다. SCT를 통해 지역적으로 스케쥴링 가능한 태스크는 전역적으로 스케쥴링이 가능하므로, 단지 지역적 스케쥴링 가능성만을 검사하면 스케쥴링 문제를 해결할 수 있도록 하였고 이를 수학적으로 증명하였다.Abstract In this paper, we present static and dynamic constraint transformation techniques for ensuring timing requirements in a distributed real-time system possessing periodically synchronized distributed local clocks. Traditional discrete clock synchronization algorithms that adjust local clocks instantaneously yield time discontinuities. Such time discontinuities lead to the loss or the gain of events, thus raising serious run-time faults.While continuous clock synchronization is generally suggested to avoid the time discontinuity problem, it incurs too much run-time overhead to be implemented in software. We propose a dynamic constraint transformation (DCT) technique which can solve the problem without modifying discrete clock synchronization algorithms. We formally prove the correctness of the DCT by showing that the DCT with discrete clock synchronization generates the same task schedule as the continuous clock synchronization.We also investigate schedulability problems that arise when imperfect local clocks are used in distributed real-time systems. We first define two notions of schedulability, global schedulability and local schedulability, and then present a static constraint transformation (SCT) technique. The SCT ensures that it is sufficient to check the schedulability of a task locally in a node with a local clock, since the global schedulability of the task is derived from its local schedulability through SCT. We formally prove the correctness of SCT.

• 한국정보처리학회논문지
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• 제4권1호
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• pp.311-323
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• 1997

본 논문에서는 게이트 레벌 소자와 스위치 레벨 소자가 함께 사용한 혼합형 조합 회로에서의 고착 고장(stuck-at fault) 검출을 위한 고장 시뮬레이션에 대하여 기술 한다. 실용적인 혼합형 회로의 고장 검출용으로 사용하기 위하여 게이트 레벨 및 정 적 스위치 레벨 회로는 물론 동적 스위치 레벨의 회로들도 처리할 수 있도록 한다. 또한, wired 논리 소자에서의 다중 신호 충돌 현상을 해결하기 위하여 새로운 6치 논 리값과 연산 규칙을 정의하여 신호 세기의 정보와 함께 사용한다. 고장 시뮬레이션의 기본 알고리즘으로는 게이트 레벨 조합 회로에서 주로 사용되는 병렬 패턴 단일 고장 전달(PPSFP:parallel pattern single fault propagation) 기법을 스위치 레벨 소자에 확장 적용한다. 마지막으로 스위치 레벨 소자로 구현된 ISCAS85 벤치 마크 회로와 실 제 혼합형 설계 회로에 대한 실험 결과를 통하여 본 연구에서 개발된 시스템의 효율 성을 입증한다.

• Structural Engineering and Mechanics
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• 제23권4호
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• pp.409-430
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• 2006

The aim of this study is to investigate the reliability of strong motion records processed by causal and acausal Butterworth filters in comparison to the results obtained from a synthetic accelerogram. For this purpose, the fault parallel component of the Bolu record of the Duzce earthquake is modeled with a sum of exponentially damped sinusoidal components. Noise-free velocities and displacements are then obtained by analytically integrating the synthetic acceleration model. The analytical velocity and displacement signals are used as a standard with which to judge the validity of the signals obtained by filtering with causal and acausal filters and numerically integrating the acceleration model. The results show that the acausal filters are clearly preferable to the causal filters due to the fact that the response spectra obtained from the acausal filters match the spectra obtained from the simulated accelerogram better than that obtained by causal filters. The response spectra are independent from the order of the filters and from the method of integration (whether analytical integration after a spline fit to the synthetic accelerogram or the trapezoidal rule). The response spectra are sensitive to the chosen corner frequency of both the causal and the acausal filters and also to the inclusion of the pads. Accurate prediction of the static residual displacement (SRD) is very important for structures traversing faults in the near-fault regions. The greatest adverse effect of the high pass filters is their removal of the SRD. However, the noise-free displacements obtained by double integrating the synthetic accelerogram analytically preserve the SRD. It is thus apparent that conventional high pass filters should not be used for processing near-fault strong-motion records although they can be reliably used for far-fault records if applied acausally. The ground motion parameters such as ARIAS intensity, HUSID plots, Housner spectral intensity and the duration of strong-motion are found to be insensitive to the causality of filters.

• 한국의류학회지
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• 제23권6호
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• pp.800-808
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• 1999

The demand for PU coated synthetic leather is increasing as a high fashion material. But it has some faults of water vapor permeability surface tacky property and static electricity. Therefore the purpose of this study was the produce of PU coated fabric added collagen with hydrophilic property and soft touch. In the PU coated fabric water vapor permeability water vaper absorption and frictional electronic voltage were investigated surface bending and compression properties were also examined by the use of KES-FB System. The followings were the results of this study. 1. There was no Cr in the collagen so that Cr was not treated in the collagen. 2. The surface and cross sectional layer of PU coated fabric with collagen were highly developed by micro porous structure. 3. The water vapor permeability of PU coated fabric was increased as collagen concentration increased. 4. The water vapor absorption of PU coated fabric was increased as collagen concentration increased. 5. The frictional electronic voltage of PU coated fabric was decreased in accordance with the increase of collagen concentration. Especially it effectively decreased by the use of only 5% collagen concentration. 6,. The bending and compression properties of PU coated fabric were increased in accordance with the increase of collagen concentration so that it became stiff. 7. The Value of MIU, SMD was decreased in accordance with the increase of collagen concentration so that the PU coated fabric became smooth.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.811-814
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• 1998

REcent research about current testing($\textrm{I}_{DDQ}$ testing) has been emphasizing that $\textrm{I}_{DDQ}$ testing in addition to the logical voltage testing is necessary to increase the fault coverage. The $\textrm{I}_{DDQ}$. testing can detect physical faults other than the classical stuck-at type fault, which affect reliability. One of the most critical issues in the $\textrm{I}_{DDQ}$ testing is to insert a built-in current sensor (BICS) that can detect abnormal static currents from the power supply or to the ground. This paper presents a new BICS for internal current testing for large CMOS logic circuits. The proposed BICS uses a single phase clock to minimize the hardware overhead. It detects faulty current flowing and converts it into a corresponding logic voltage level to make converts it into a corresponding logic voltage level to make it possible to use the conventional voltage testing techniqeus. By using current mirroring technique, the proposed BICS can work at very high speed. Because the proposed BICS almost does not affects normal operation of CUT(circuit under test), it can be used to a very large circuit without circuit partitioning. By altenating the operational modes, a circuit can be $\textrm{I}_{DDQ}$-tested as a kind of self-testing fashion by using the proposed BICS.