• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.6
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• pp.259-263
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• 2001

The continuum model of transient point defect dynamics to predict the concentrations of interstitial and vacancy is established by estimating expressions for the thermophysical properties of intrinsic point defects. And the point defect distribution in a Czochralski-grown 200 mm silicon crystal and the location of oxidation-induced stacking fault ring(OiSF-ring) created during the cooling of crystals are calculated by using the numerical analysis. The purpose of this paper is to show that his approach lead to predictions that are consistent with experimental results. Predicted point defect distributions by transient point defect dynamic analysis are in good qualitative agreement with experimental data under widely and abruptly varying crystal pull rates when correlated with the position of the OiSF-ring .

• Korean Journal of Materials Research
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• v.19 no.8
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• pp.447-451
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• 2009

The long-period stacking order (LPSO) structures and stacking faults (SFs) in rapidly solidified powder metallurgy (RS P/M) $Mg_{97}Zn_1Y_2$ alloy were investigated by high resolution transmission electron microscopy (HRTEM) observations. The 18R-type LPSO structure with a stacking sequence of ACBCBCBACACACBABAB and a period of 4.86 nm was observed in the as-extruded RS P/M $Mg_{97}Zn_1Y_2$ alloy. After annealing at 773 K for 5 hr, the 18R-type LPSO structure was transformed to the 14H-type LPSO structure with a stacking sequence of ABABABACBCBCBC and a period of 3.64 nm. The 24R-type LPSO structure containing 24 atomic layers of ABABABABCACACACABCBCBCBC with period of 6.18 nm coexists with the 14H-type LPSO structure in the same grains. The LPSO structures contain intrinsic Type II SFs such as BCB/CABA and ABA/CBCB stacking sequences of a closely packed plane.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1510-1512
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• 2000

Due to the shrinking of the chip size and increasing of the complexity in the modern electronic devices. the defect of wafer are so important to decide the yield in the device process. The engineers has studied the wafer defects and the characteristics. They published lots of the experimental methods. I did an experiment the gettering effect of the defects due to the high temperature and the long time diffusion. Actually, As the thickness of the wafer backside polysilicon is thicker and the diffusion time is faster. the defects on the wafer are decreased. The polysilicon gram boundaries of the wafer backside played an important part as the defect gettering site.

• Korean Journal of Materials Research
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• v.26 no.11
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• pp.656-661
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• 2016

4H- and 6H-SiC grown by physical vapor transport method were investigated by transmission electron microscopy (TEM). From the TEM diffraction patterns observed along the [11-20] zone axis, 4H- and 6H-SiC were identified due to their additional diffraction spots, indicating atomic stacking sequences. However, identification was not possible in the [10-10] zone axis due to the absence of additional diffraction spots. Basal plane dislocations (BPDs) were investigated in the TEM specimen prepared along the [10-10] zone axis using the two-beam technique. BPDs were two Shockley partial dislocations with a stacking fault (SF) between them. Shockley partial BPDs arrayed along the [0001] growth direction were observed in the investigated 4H-SiC. This arrayed configuration of Shockley partial BPDs cannot be recognized from the plan view TEM with the [0001] zone axis. The evaluated distances between the two Shockley partial dislocations for the investigated samples were similar to the equilibrium distance, with values of several hundreds of nanometers or even values as large as over a few micrometers.