• Journal of Mechanical Science and Technology
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• v.19 no.5
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• pp.1065-1071
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• 2005

In this study, residual stress distribution in multi-stacked film by MEMS (Micro-Electro Mechanical System) process is predicted using Finite Element method (FEM). We evelop a finite element program for residual stress analysis (RESA) in multi-stacked film. The RESA predicts the distribution of residual stress field in multi-stacked film. Curvatures of multi­stacked film and single layers which consist of the multi-stacked film are used as the input to the RESA. To measure those curvatures is easier than to measure a distribution of residual stress. To verify the RESA, mean stresses and stress gradients of single and multi layers are measured. The mean stresses are calculated from curvatures of deposited wafer by using Stoney's equation. The stress gradients are calculated from the vertical deflection at the end of cantilever beam. To measure the mean stress of each layer in multi-stacked film, we measure the curvature of wafer with the left film after etching layer by layer in multi-stacked film.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.184-187
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• 2002

In this work, the electrical characteristics of organic thin film transistors with the stacked organic gate insulators have been studied. PVP(Polyvinylphenol) and polystyrene were used as gate insulating materials. Both the high dielectric constant of PVP and better insulating capability of polystyrene were compensatorily adopted in two different stacking orders of PVP-polystyrene and polystyrene-PVP. The output characteristics of the device with the stacked gate insulator showed substantial improvement compared with those of the devices with either PVP or polystyrene gate insulator: Furthermore, these stacked organic gate insulators can differently affect the TFT characteristics with the stacking orders. The electrical properties of TFTs with organic gate insulators stacked in different orders are discussed.

• 한국신재생에너지학회:학술대회논문집
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• 2007.06a
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• pp.326-329
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• 2007

$CuInS_{2}$ thin films were synthesized by sulpurization of Cu/In Stacked elemental layer deposited onto glass Substrates by vacuum furnace annealing at temperature 200[$^{\circ}C$]. And structural and electrical properties were measured in order to certify optimum conditions for growth of the ternary compound semiconductor $CuInS_{2}$ thin films with non-stoichiometry composition. $CuInS_{2}$ thin film was well made at the heat treatment 200[$^{\circ}C$] of SLG/Cu/ln/S stacked elemental layer which was prepared by thermal evaporator, and chemical composition of the thin film was analyzed nearly as the proportion of 1 : 1 : 2. Physical properties of the thin film were investigated at various fabrication conditions substrate temperature, annealing and temperature, annealing time by XRD, FE-SEM and Hall measurement system. At the same time, carrier concentration, hall mobility and resistivity of the thin films was $9.10568{\times}10^{17}$ [$cm^{-3}$], 312.502 [$cm^{2}/V{\cdot}s$] and $2.36{\times}10^{-2}$ [${\Omega}{\cdot}cm$], respectively.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1546-1548
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• 2002

In this paper, the electrical characteristics of pentacene thin film transistors(TFTs) with stacked and surface-treated gate insulators have been investigated. The semiconductor layer of pentacene was thermally evaporated onto the stacked gate insulators. For the gate insulating materials. PVP(PolyvinylPhenol) and polystyrene were spin-coated with two different stacking orders, PVP-polystyrene and polystyrene-PVP. Rapid solvent evaporation during the spin-coating processes of these insulating layers produces non-equilibrium phase morphologies accompanied by surface undulations on gate insulator interfaces. This non-equilibrium phase morphology affects the growth mode of the subsequent pentacene layer. Therefore, in order to smoothen the gate dielectric surfaces, gate dielectric surfaces were rubbed laterally along the direction from the drain to the source TFTs with with stacked and surface-treated gate insulators have provided improved operational characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.118-119
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• 2007

High performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide semiconductor (CMOS) inverters with a high quality laser crystallized channel were fabricated. Low temperature crystallization methods of a-Si film using the excimer-laser annealing (ELA) and sequential lateral solidification (SLS) were performed. The NMOS thin-film-transistor (TFT) at lower layer of CMOS was fabricated on oxidized bulk Si substrate, and the PMOS TFT at upper layer of CMOS was fabricated on interlayer dielectric film. The 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and was enough for the vertical integrated CMOS applications.

• Current Photovoltaic Research
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• v.8 no.3
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• pp.94-101
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• 2020

This study was trying to focus on achieving high efficiency of multi junction solar cell with thin film silicon solar cells. The proposed thin film Si-Ge/c-Si tandem junction solar cell concept with a combination of low-cost thin-film silicon solar cell technology and high-efficiency c-Si cells in a monolithically stacked configuration. The tandem junction solar cells using amorphous silicon germanium (a-SiGe:H) as an absorption layer of upper sub-cell were simulated through ASA (Advanced Semiconductor Analysis) simulator for acquiring the optimum structure. Graded Ge composition - effect of E_g profiling and inserted buffer layer between absorption layer and doped layer showed the improved current density (J_sc) and conversion efficiency (η). 13.11% conversion efficiency of the tandem junction solar cell was observed, which is a result of showing the possibility of thin film Si-Ge/c-Si tandem junction solar cell.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.261-262
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• 2006

$CuInS_2$ thin films were synthesized by sulpurization of Cu/In Stacked elemental layer deposited onto glass Substrates by vacuum furance annealing at temperature 200[$^{\circ}C$]. And structural and electrical properties were measured in order to certify optimum conditions for growth of the ternary compound semiconductor $CuInS_2$ thin films with non-stoichiometry composition. $CuInS_2$ thin film was well made at the heat treatment 200[$^{\circ}C$] of SLG/Cu/In/S stacked elemental layer which was prepared by thermal evaporator, and chemical composition of the thin film was analyzed nearly as the proportion of 1:1:2. Physical properties of the thin film were investigated at various fabrication conditions substrate temperature, annealing and temperature, annealing time by XRD, FE-SEM and hall measurement system. At the same time, carrier concentration, hall mobility and resistivity of the thin films was $9.10568{\times}10^{17}[cm^{-3}]$, 312.502 [$cm^2/V{\cdot}s$] and $2.36{\times}10^{-2}[{\Omega}{\cdot}cm]$, respectively.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1268-1269
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• 2008

$CuInS_2$ thin films were fabricated by sulpurization of Cu/In Stacked elemental layer deposited onto glass substrates by vacuum annealing at various temperatures. And structural and electrical properties were measured in order to certify optimum conditions for growth of the ternary compound semiconductor $CuInS_2$ thin films by composition ratio. Physical properties of the thin film were investigated at various fabrication conditions; substrate temperature, annealing temperature and annealing time by XRD, FE-SEM and hall measurement system. $CuInS_2$ thin film was well made at the heat treatment 200[$^{\circ}C$] of SLG/Cu/In/S stacked elemental layer.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.9
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• pp.29-35
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• 1992

Dielectric thin film of N/O (Si$_{3}N_[4}/SIO_{2}$) for high density stacked dynamic-RAM cell was formed by LPCVD and oxidation(Dry & pyrogenic oxidation methods) of the top Si$_{3}N_[4}$ film. The thickness, structure and composition of this film were measured by ellipsometer, high frequency C-V meter, high resolution TEM, AES, and SIMS. The thickness limit of Si$_{3}N_[4}$ film in making thin N/O structure layer was 7nm. In this experiment, the film with thinner than 7nm was not thick enough as oxygen diffusion barrier, and oxygen punched through the film and interfacial oxidation occurred at the phase boundary between Si$_{3}N_[4}$ and polycrystalline silicon electrode.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.97-97
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• 2013

Recently, Cu2ZnSn(S,Se)4 (CZTSS), which is one of the In- and Ga- free absorber materials, has been attracted considerable attention as a new candidate for use as an absorber material in thin film solar cells. The CZTSS-based absorber material has outstanding characteristics such as band gap energy of 1.0 eV to 1.5 eV, high absorption coefficient on the order of 104 cm-1, and high theoretical conversion efficiency of 32.2% in thin film solar cells. Despite these promising characteristics, research into CZTSS based thin film solar cells is still incomprehensive and related reports are quite few compared to those for CIGS thin film solar cells, which show high efficiency of over 20%. I will briefly overview the recent technological development of CZTSS thin film solar cells and then introduce our research results mainly related to sputter based process. CZTSS thin film solar cells are prepared by sulfurization of stacked both metallic and sulfide precursors. Sulfurization process was performed in both furnace annealing system and rapid thermal processing system using S powder as well as 5% diluted H2S gas source at various annealing temperatures ranging from $520^{\circ}C$ to $580^{\circ}C$. Structural, optical, microstructural, and electrical properties of absorber layers were characterized using XRD, SEM, TEM, UV-Vis spectroscopy, Hall-measurement, TRPL, etc. The effects of processing parameters, such as composition ratio, sulfurization pressure, and sulfurization temperature on the properties of CZTSS absorber layers will be discussed in detail. CZTSS thin film solar cell fabricated using metallic precursors shows maximum cell efficiency of 6.9% with Jsc of 25.2 mA/cm2, Voc of 469 mV, and fill factor of 59.1% and CZTS thin film solar cell using sulfide precursors shows that of 4.5% with Jsc of 19.8 mA/cm2, Voc of 492 mV, and fill factor of 46.2%. In addition, other research activities in our lab related to the formation of CZTS absorber layers using solution based processes such as electro-deposition, chemical solution deposition, nano-particle formation will be introduced briefly.