• Journal of the Korean Society for Precision Engineering
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• v.15 no.3
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• pp.38-49
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• 1998

The 3rd generation optical pick-up used popularly in resent years is composed of many optical and electronic components such as laser diode, photo diode, beam splitter, objective lens, grating lens, concave lens, collimator lens etc. Therefore, the design of its optical system and its main base which the said optical and electronic components are set on, is complicated and needs high precision. Its assembly and adjustment in the production line is also difficult. This complication and the demand of high precision get its production cost to be high and its reliability to be low. In this paper, the 4th generation optical pick-up is designed and developed, with the hologram device which laser diode. photo diode, beam splitter. and grating lens are integrated in. This optical pick-up reduces the number of points of adjustment by 3, compared with the 3rd generation optical pick-up of which the number of points of adjustment is 6. This optical pickup also decreases by 4 the number of points of W bonding to have bad influence on environmental reliability, decreases by about 10 the number of parts, and establishes about 20% cost-down of material cost, compared with the 3rd generation optical pick-up.

• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.61-64
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• 2007

V-groove device was fabricated for precision coupling of planar optical splitter and optical fibers. V-groove was made through select wet etching of Si wafer by using KOH solution. Etching rate and surface roughness were checked, changing KOH composition(10, 20, 30, 33, 40 wt.%) and etching temperature (50, 60, 70, $80^{\circ}C$) to fabricate V-groove device effectively. Etching rate was the fastest as $1.84\;{\mu}m/min$ in case of etching by 20 wt.% KOH on $80^{\circ}C$, surface roughness was the best in case of etching by 33 wt. % KOH on $80^{\circ}C$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.4
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• pp.499-508
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• 1993

This paper has dealt with the design methods and the analysis of frequency characteristics for the power splitters with ferrite toroids, which are extensively used in CATV and/or MATV systems. The theoretical design methods and frequency characteristics of the prototype Wilkinson's 2-way power divider have been reviewed in lumped-element circuits form. On the basis of the design theory of the prototype Wilkinson's power divider, the method compensating of the prototype Wilkinson's power divider has been proposed by means of adding matching transformers. Thus, it has been shown that the theoretical frequency characteristics of the compensated power splitter are improved drastically in comparison with the prototype Wilkinson's power divider. Furthermore, the practical measurements of the frequency characteristics for the fabricated circuits show agreements with the theoretical results, and hence, the validity of the proposed design and analysis methods has been confirmed.

• Transactions of the Korean Society of Automotive Engineers
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• v.6 no.6
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• pp.132-141
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• 1998

Particle image velocimetry(PIV), a planar measuring technique, is an efficient tool for studying the complicated flow field such as in-cylinder flow, and intake port flow. PIV can be also used for analyzing the integral length scale of turbulence, which is a measure of the size of the large eddies that contain most of the turbulence kinetic energy. In this study, dual color scanning PIV was designed and demonstrated by using a rotating mirror and a beam splitter. This PIV system allowed enlargement of flexibility in the intensity of vectors to be calculated by spatial filtering technique, even in combustion chamber with high velocity gradient and high vorticity$({\sim}1000s^{-1})$. A new color image processing algorithm was developed, which was used to find the direction of particle movement directly from the digital image. These measuring techniques were successfully applied to obtaining the turbulence intensity (~0.1m/s) and the turbulent integral length scale of vorticity(~1mm).

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.811-816
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• 2011

In this paper, we propose a optimal design using the Evolution Strategy of a high gain $4\times4$ array antenna that have the resonant frequency of a 19.05GHz with 18.86GHz~19.26GHz bandwidth. The proposed array antenna structure is designed to be allocated equally electric power by microstrip patch power splitter. Thus the optimal array antenna with power splitter are determined by using an optimal design program based on the evolution strategy. To achieve this, an interface program between a commercial EM analysis tool and the optimal design program is constructed for implementing the evolution strategy technique that seeks a global optimum of the objective function through the iterative design process consisting of variation and reproduction. The simulation result of $4\times4$ array antenna is confirmed that the Gain is 19.36 dBi at resonance frequency 19.05GHz.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2008.03a
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• pp.168-172
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• 2008

Three different geometry shapes of the blade leading edge in a centrifugal compressor were investigated in this paper. Numerical simulation was done to analyze the effect of the leading edge shape on the performance of the centrifugal compressor. The result shows that compared to the blunt leading edge, the circular leading edge will raise the chocking mass flow. The pressure ratio and efficiency will increase obviously. Using elliptical leading edge will get a further improvement on the performance than circular leading edge. The analysis of the flow field shows that the leading edge often causes flow separation near the inlet; using circular leading edge and elliptical leading edge will reduce the separation. What's more, using circular and elliptical leading edge will also reduce the wake loss near the outlet of the impeller. In a centrifugal compressor, using circular or elliptical leading edge on the splitter will improve the pressure loading distribution of main blade near the position of the splitter leading, which will increase the pressure ratio.

• Korean Journal of Optics and Photonics
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• v.14 no.6
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• pp.657-662
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• 2003

Optimum Hamming apodized acousto-optic 2${\times}$2 add/drop multiplexers, using SiO$_2$ film loaded acoustic waveguide with angular offset to the Ti:LiNbO$_3$ waveguide, were fabricated. The four-port device consists of two input waveguides, a polarization beam splitter (PBS), two polarization conversion/acoustooptic tuning waveguide sections, a second PBS and two output waveguides. Insertion loss <7.1 ㏈ has been obtained and side-lobe of -19 ㏈ for -32 ㎽ RF driving power has been realized. Add/drop performance has been confirmed and a linear tuning rate of 8.1 nm/MHz and a 3 ㏈ spectral width of -1.5 nm were demonstrated.

• Membrane Journal
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• v.24 no.5
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• pp.409-415
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• 2014

This study is aimed to separate propylene and propane using membrane process instead of NCC(Naphtha Cracking Center) $C_3$ splitter. Membrane process is a low energy consumption and eco-friendly process while $C_3$ splitter requires high energy consumption in petrochemical processes. In this study, high performance facilitated transport membrane (FTM) is used for propylene/propane separation. FTM module was prepared on top of porous polyetherimide hollow fiber using PVP/$AgBF_4$/TCNQ. We developed simulation program predicting the membrane separation properties under operation conditions. Separation properties of FTM module for propylene and propane were obtained from the simulation program based on the pure gas permeation data. Based on these results, it is predicted that an one-stage membrane process provides 99.5% of propylene at permeate side from a binary gas mixture of 95/5 vol% $C_3H_6$ / vol% $C_3H_8$ supplied as a feed gas.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.