• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.23-29
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• 2009

Blob detection is an essential ingredient process in some computer applications such as intelligent visual surveillance. However, previous blob detection algorithms are still computationally heavy so that supporting real-time multi-channel intelligent visual surveillance in a workstation or even one-channel real-time visual surveillance in a embedded system using them turns out prohibitively difficult. In this paper, we propose a fast and precise blob detection algorithm for visual surveillance. Blob detection in visual surveillance goes through several processing steps: foreground mask extraction, foreground mask correction, and connected component labeling. Foreground mask correction necessary for a precise detection is usually accomplished using morphological operations like opening and closing. Morphological operations are computationally expensive and moreover, they are difficult to run in parallel with connected component labeling routine since they need much different processing from what connected component labeling does. In this paper, we first develop a fast and precise foreground mask correction method utilizing on neighbor pixel checking which is also employed in connected component labeling so that the developed foreground mask correction method can be incorporated into connected component labeling routine. Through experiments, it is verified that our proposed blob detection algorithm based on the foreground mask correction method developed in this paper shows better processing speed and more precise blob detection.

• International journal of advanced smart convergence
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• v.10 no.2
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• pp.175-186
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• 2021

We have studied the speed regulation of the permanent magnet synchronous motor (PMSM) servo system in this paper. To optimize the PMSM servo system's speed-control performance with disturbances, a non-linear speed-control technique using a back-propagation neural network (BP-NN) algorithm forthe controller design of the PMSM speed loop is introduced. To solve the slow convergence speed and easy to fall into the local minimum problem of BP-NN, we develope an improved BP-NN control algorithm by limiting the range of neural network outputs of the proportional coefficient Kp, integral coefficient Ki of the controller, and add adaptive gain factor β, that is the internal gain correction ratio. Compared with the conventional PI control method, our improved BP-NN control algorithm makes the settling time faster without static error, overshoot or oscillation. Simulation comparisons have been made for our improved BP-NN control method and the conventional PI control method to verify the proposed method's effectiveness.

• Atmosphere
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• v.17 no.4
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• pp.421-433
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• 2007

We have investigated the seasonal characteristics of surface turbulent fluxes observed at Ieodo Ocean Research Station from 2005 to 2006. Both 10Hz and 30 minutes flux data are quality controled, and tilt correction is performed in 10Hz data before quality control. The turbulent fluxes of open sea shows clear seasonal variations, though diurnal variations are barely shown. The seasonal ratio of stable and unstable conditions are closely related to the temperature difference between sea surface and air. In stable and semi-stable condition, latent and sensible heat fluxes have very small values without any relationship with wind speed. Though friction velocity shows slightly increasing trend with wind speed, it has many outliers. In unstable condition, turbulent fluxes increased with wind speed. Especially, latent heat flux increased rapidly during DJF. The latent heat flux at high wind speeds is more scatter.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.3
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• pp.246-251
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• 2012

This paper proposes a new position compensation method for misaligned Hall-effect sensors of BLDCM(Brushless DC Motor). If the Hall-effect sensors are installed at wrong position, the exact rotor position cannot be obtained. Therefore, when the BLDCM is controlled with this wrong position, the torque ripple can be increased and the average torque also decreases. The back-EMF of BLDCM can be obtained by using the voltage equation and by multiplying the back-EMF constant and rotor speed. At a constant speed, the estimated back-EMF by using the multiplication of the back-EMF constant and rotor speed is constant, but the estimated back-EMF from the voltage equation decreases at the commutation point because the line-to-line back-EMF of two conducting phases is start to decrease at this point. Therefore, by using the difference between these two estimated back-EMFs, the commutation point of the phase current can be determined and position compensation can be carried out. The proposed position correction method doesn't require additional hardware circuit and can be easily implemented. The validity of the proposed position compensation method is verified through several experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.211-218
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• 2005

Switched Reluctance Motor(SRM) offers the advantages of simple and robust motor construction, high speed and high efficiency over a wide operating range of torque and speed, excellent controllability. However SRM has the disadvantages of high current harmonics, and low power factor because the required output of speed and torque is produced by the discontinuous and loss of power system, and brings about the incorrect operation of electronic system. This paper deals with an energy efficient converter fed SRM system with the reduced harmonics and improved power factor. The validity of the proposed scheme is verified via experiments. We are implemented the proposed control system using 80C196KC micro-controller.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.41-44
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• 2013

As appearance of high-quality service such as UDTV application, high-speed and high-capacity communication services are required. For this, communication systems increase the data processing speed and use various error correction techniques. In this paper, we implement the Viterbi decoder applied in 1000BASE-T with 4 pairs UTP cable. The minimum operating speed of the Viterbi decoer should be more than 125 MHz because 125 MHz PAM-5 signal is transmitted on each pair of cables in 1000BASE-T. To do this, we implement the decoder by using the pipeline and parallel processing and verify the operation with 125 MHz by using a logic analyzer. Finally, we will show that the decoder recovers the original data for the added random error data.

• Electronics and Telecommunications Trends
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• v.38 no.5
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• pp.34-50
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• 2023

Quantum error correction is a key technology for achieving fault-tolerant quantum computation. Finding the best decoding solution to a single error syndrome pattern counteracting multiple errors is an NP-hard problem. Consequently, error decoding is one of the most expensive processes to protect the information in a logical qubit. Recent research on quantum error decoding has been focused on developing conventional and neural-network-based decoding algorithms to satisfy accuracy, speed, and scalability requirements. Although conventional decoding methods have notably improved accuracy in short codes, they face many challenges regarding speed and scalability in long codes. To overcome such problems, machine learning has been extensively applied to neural-network-based error decoding with meaningful results. Nevertheless, when using neural-network-based decoders alone, the learning cost grows exponentially with the code size. To prevent this problem, hierarchical error decoding has been devised by combining conventional and neural-network-based decoders. In addition, research on quantum error decoding is aimed at reducing the spacetime decoding cost and solving the backlog problem caused by decoding delays when using hardware-implemented decoders in cryogenic environments. We review the latest research trends in decoders for quantum error correction with high accuracy, neural-network-based quantum error decoders with high speed and scalability, and hardware-based quantum error decoders implemented in real qubit operating environments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.48-55
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• 2009

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.

• Journal of Software Assessment and Valuation
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• v.15 no.1
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• pp.103-107
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• 2019

Recently, many technologies have been developed to realize low power high speed digital data communication and one of them is related to duty cycle correction. In this paper, a low-area duty cycle correction circuit for a voltage-controlled ring generator is proposed. The duty cycle correction circuit is a circuit that corrects the duty cycle using a 180 degree phase difference of a voltage controlled ring oscillator. The proposed low-area duty cycle circuit changes a conventional flip-flop to a true single phase clocking (TSPC) flip-flop And a low-area high-performance circuit is realized. By using TSPC flip-flop instead of general flip-flop, it is possible to realize low-area circuit compared to existing circuit, and it is expected to be used for high-performance circuit for low-power because it is easy to operate at high speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.