• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.65-70
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• 1998

In this paper, we will to check and to correct mis-recognized word using Eojeol information. First, we divided into 16 classes that constituents in a Eojeol after we analyzed Korean statement into Eojeol units. Eojeol-Constituent state diagram constructed these constitutents, find the Left-Right Connectivity Information. As analogized the speech of connectivity information, reduced the number of cadidate words and restricted case of morphological analysis for mis-recognition Eojeol. Then, we improved correction speed uisng heuristic information as the adjacency information for Eojeol each other. In the correction phase, construct Reverse-Order Word Dictionary. Using this, we can trace word dictionary regardless of mis-recongnition word position. Its results show that improvement of recognition rate from 97.03% to 98.02% and check rate, reduction of chadidata words and morpholgical analysis cases.

• Journal of Power Electronics
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• v.10 no.3
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• pp.293-299
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• 2010

In this paper, a single-phase PFC (Power Factor Correction) dual boost converter based on input voltage estimation is studied for DC inverter air conditioner. It is focused on improving input power factor and power quality to satisfy the recent harmonic current regulation standards. Furthermore the input voltage estimation is introduced for price competitive products. A low cost and reasonable control system is implemented using a specified high-speed 32-bit microprocessor. Their effectiveness are verified through theoretical analysis and experiments.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1173-1176
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• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing cell array is proposed. It has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram. The constraints' length of trellis diagram is connected circularly so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• Journal of the Korea Society of Computer and Information
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• v.22 no.8
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• pp.15-23
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• 2017

In this paper, the block reweighting and global offset initialization methods are proposed to complement the improved IRLMS algorithm which is the effective algorithm in registration based SBNUC algorithm. Proposed block weighting method reweights the error map whose abnormal data are excluded. The global offset initialization method compensates the global nonuniformity initially. The ordinary registration based SBNUC algorithm is hard to compensate global nonuniformity because of low scene motion. We employ the proposed methods to improved IRLMS algorithm, and apply it to real-world infrared raw image stream. The result shows that new implementation provides 3.5~4.0dB higher PSNR and convergence speed 1.5 faster then the improved IRLMS algorithm.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.5
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• pp.426-431
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• 2008

In this paper, an improved AE system for digital still camera is proposed. AE system is auto exposure system to maintain optimized brightness of output image. But there is limitation for mobile devices to get high quality image with the conventional AE algorithm, because of organizational restriction of system. The conventional research has been studied only electronic shutter and AGC on the AE algorithm. In this paper, we suggest new AE algorithm included target setting, frame delay, Gamma Correction as well as electronic shutter and AGC to get high quality image. The proposed algorithm show improved result at control speed and ability of luminance expression.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• 한국신재생에너지학회:학술대회논문집
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• 2008.10a
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• pp.278-281
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• 2008

In these days the installation of wind turbines or wind parks includes a high financial risk. So for the planning and the constructing of wind farms, long-term data of wind speed and wind direction is required. However, in most cases only few data are available at the designated places. Traditional Measure-Correlate-Predict (MCP) can extend this data by using data of nearby meteorological stations. But also Neural Networks can create such long-term predictions. The key issue of this paper is to demonstrate the possibility and the quality of predictions using Neural Networks. Thereto this paper compares the results of different MCP Models and Neural Networks for creating long-term data with various indexes.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2388-2390
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• 2002

Small type electric energy saving system is proposed in this paper. The system improves power factor fastly according to load variation of each customer. Phases of voltage and current are detected as 1[ms] unit. Phase coincident algorithm is applied for power factor improvement. Capacitance is controlled for optimal power factor correction. Series reactor is controlled for harmonics reduction. Non-contact device is used for fast response and long life. Test result shows the effect of this system. Power factor of 40[W] electric fan is improved from 95[%] to 100[%]. In the case of electric light, power factor is improved from 82[%] to 100[%]. Response time for load variation is less than 1[ms].

• Journal of electromagnetic engineering and science
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• v.17 no.1
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• pp.39-43
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• 2017

In this paper, a systematic and statistical calibration technique was implemented to calibrate a high-speed signal converting system containing multiple digital-to-analog converters (DACs). The systematic error (especially the imbalance between DACs) in the current combining network of the multi-DAC system was modeled and corrected by calculating the path coefficients for individual DACs with wideband reference signals. Furthermore, by applying a Kalman filter to suppress noise from quantization and clock jitter, accurate coefficients with minimum noise were identified. For correcting an arbitrary waveform generator with two DACs, a co-simulation platform was implemented to estimate the system degradation and its corrected performance. Simulation results showed that after correction with 4.8 Gbps QAM signal, the signal-to-noise-ratio improved by approximately 4.5 dB and the error-vector-magnitude improved from 4.1% to 1.12% over 0.96 GHz bandwidth.

• Journal of International Society for Simulation Surgery
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• v.1 no.2
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• pp.83-86
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• 2014

Purpose This paper was purposed to suggest the method to produce the supportive helmet (head correction) for the infants who are suffering from plagiocephaly and to evaluate the level of transformation through 3D model. Method Either of CT or X-ray restored images has been used in making the supportive helmet (Head correction) in general, but these methods of measuring have problems in cost and safety. 3D surface measurement technology was suggested to solve such matters. Results It was to design the transformed model of the head within 0.7cm in average by scanning the surface of head and performing 3D restoration with marching cube and the changing rate of the head was compared in numerical data with 3D model. Conclusion The suggested methods displayed the better performance than the conventional method in respect of the speed and cost.