• Electrical & Electronic Materials
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• v.10 no.8
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• pp.794-799
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• 1997

Poly-Si films have been prepared by solid phase crystallization of LPCVD(low-pressure CVD) amorphous silicon. The crystallinity of poly-Si films has been derived from UV reflectance spectrum and lies in the range between 70% and 80% . From XRD measurement the peak at 28.2$^{\circ}$from (111) plane is dominantly detected in the SPC poly-Si films, The average grain size of poly-Si film is determined by the image of SEM and varies from 4000 $\AA$ to 8000$\AA$. The electrical conductivity of as-deposited amorphous silicon film is about 2.5$\times$10$^{-7}$ ($\Omega$.cm)$^{-1}$ , and 3~4$\times$10$^{-6}$ ($\Omega$.cm)$^{-1}$ of room temperature conductivity is the SPC poly-Si films. The conductivity activation energies are 0.5~0.6 eV or the 500$\AA$-thick poly-Si films.

• Journal of the Korean Applied Science and Technology
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• v.28 no.3
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• pp.306-312
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• 2011

In this study, we are crystallized to the low density polyethylene (LDPE) micro-particles in $n$-dodecanol solution by thermally induced phase separation(TIPS) method. The Low density polyethylene micro-particles is used in a wide variety of polymer coatings and industrial application. The utility of that for a particular application depends on a number of factors such as the particle size and distribution, and chemical composition of the materials. However, there are still needs for new methods of preparation which will provide the structure with unique sizes. The widely used processes for micro-size particles are crystallization method and thermally induced phase separation. TIPS process based on the phase separation mechanism was performed for the LDPE system which undergoes liquid-solid phase separation. Effects of various operating parameters were examined on the structure variation of the particles. Professionality, take-up speed and crystallization rate depended on temperature and concentration of polymer in solution.

• Journal of Korean Vacuum Science & Technology
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• v.2 no.1
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• pp.49-54
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• 1998

The effect of deposition paratmeters on the solid-phase crystallization of amorphous silicon films deposited by plasma-enhanced chemical vapor deposition has been investigated by x-ray diffraction. The amorphous silicon films were prepared on Si(100) wafers using SiH4 gas with and without H2 dilution at the substrate temperatures between 12$^{\circ}C$ and 38$0^{\circ}C$. The R. F. powers and the deposition pressures were also varied. After crystallizing at $600^{\circ}C$ for 24h, the films exhibited (111), (220), and (311) x-ray diffraction peaks. The (111) peak intensity increased as the substrate temperature decreased, and the H dilution suppressed the crystallization. Increasing R.F. powers within the limits of etching level and increasing deposition pressures also have enhanced the peak intensity. The peak intensity was closely related to the deposition rate, which may be an indirect indicator of structural disorder in amorphous silicon films. Our results are consistent with the fact that an increase of the structural disorder I amorphous silicon films enhances the grain size in the crystallized films.

• Journal of Korean Vacuum Science & Technology
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• v.2 no.2
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• pp.97-100
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• 1998

We have investigated the effects of crystalline activation on solid phase crystallization (SPC) of amorphous silicon (a-Si) thin films. Wet blasting and self ion implantation were employed as the activation treatments to induce macro or micro crystalline damages on deposited a-Si films. Low temperature and larger grain crystallization were obtained by the applied two-step activation. High degree of crystallinity was also observed on both furnace and rapid SPC. crystalline activations showed the promotion of nucleation on the activated regions and the retardation of growth in an amorphous matrix in SPC. The observed behavior of two-step SPC was strongly dependent on the applied activation and annealing processes. It was also found that the diversified effects by macro and micro activations on the SPC were virtually diminished as the annealing temperature increased.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.766-772
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• 2011

Amorphous Si (a-Si) thin films of $p^+/p^-/n^+$ were deposited on $Si_3N_4$/glass substrate by using a plasma enhanced chemical vapor deposition (PECVD) method. These films were annealed at various temperatures and for various times by using a rapid thermal process (RTP) equipment. This step was added before the main thermal treatment to make the nuclei in the a-Si thin film for reducing the process time of the crystallization. The main heat treatment for the crystallization was performed at the same condition of $600^{\circ}C$/18 h in conventional furnace. The open-circuit voltages ($V_{oc}$) were remained about 450 mV up to the nucleation condition of 16min in the nucleation RTP temperature of $680^{\circ}C$. It meat that the process time for the crystallization step could be reduced by adding the nucleation step without decreasing the electrical property of the thin film Si for the solar cell application.

• Journal of Convergence for Information Technology
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• v.9 no.5
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• pp.117-124
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• 2019

This paper discusses recent trends in the fabrication of semiconducting materials among the components of thin film transistors used in AMOLED display. In order to obtain a good semiconductor film, it is necessary to change the amorphous silicon into polycrystalline silicon. There are two ways to use laser and heat. Laser-based methods include sequential lateral solidification (SLS), excimer laser annealing (ELA), and thin-beam directional crystallization (TDX). Solid phase crystallization (SPC), super grain silicon (SGS), metal induced crystallization (MIC) and field aided lateral crystallization (FALC) were crystallized using heat. We will also study research for manufacturing large AMOLED displays.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.05a
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• pp.114-114
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• 1998

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.89-89
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• 1995

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.285.1-285.1
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.279.1-279.1
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• 2016

박막 트랜지스터 (thin film transistor, TFT)는 고밀도, 대면적화로 높은 전자의 이동도가 요구되면서, 비정질 실리콘 (a-Si)에서 다결정 실리콘 (poly-Si) TFT 로 연구되었다. 이에 따라 비정질 실리콘에서 결정질 실리콘으로의 상변화에 대한 결정화 연구가 활발히 진행되었다. 또한, 박막 태양전지 분야에서도 유리기판 위에 비정질 층을 증착한 후에 열처리를 통해 상변화하는 고상 결정화 (solid-phase crystallization, SPC) 기술을 적용하여, CSG (thin-film crystalline silicon on glass) 태양전지를 보고하였다. 이러한 비정질 실리콘 층의 결정화 기술을 결정질 실리콘 태양전지 에미터 형성 공정에 적용하고자 한다. 이 때, 플라즈마화학증착 (Plasma-enhanced chemical vapor deposition, PECVD) 장비로 증착된 비정질 실리콘 층의 열처리를 통한 결정화 정도가 중요한 요소이다. 따라서, 비정질 실리콘 층의 결정화에 영향을 주는 인자에 대해 연구하였다. 비정질 실리콘 증착 조건(H2 가스 비율, 도펀트 유무), 실리콘 기판의 결정방향, 열처리 온도에 따른 결정화 정도를 엘립소미터(elipsometer), 투과전자현미경 (transmission electron microscope, TEM), 적외선 분광기 (Fourier Transform Infrared, FT-IR) 측정을 통하여 비교 하였다. 이를 기반으로 결정화 온도에 따른 비정질 실리콘의 결정화를 위한 활성화 에너지를 계산하였다. 비정질 실리콘 증착 조건 보다 기판의 결정방향이 결정화 정도에 크게 영향을 미치는 것으로 확인하였다.