• Journal of Welding and Joining
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• v.25 no.3
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• pp.45-50
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• 2007

The present study is devoted to investigate the transient flow and to estimate the filling time fur underfill process by using the numerical model established on the fluid momentum equation. For optimization of the design and selection of process parameters, this study extensively presents an estimation of the filling time in the view points of some important factors related to underfill materials and flip-chip geometry. From the results, we conclude that the filling time changes with respect to the under fill materials because of different viscosity, surface tension coefficient and contact angle. It reveals that, as the gap height increases, the filling time decreases substantially, and goes to the saturated values.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.227-228
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• 2007

본 연구에서는 플립칩 범프를 형성하는 여러 가지 방법 중 전해도금을 이용하여 Sn-0.7wt%Cu 솔더 범프를 형성 하고자 하였다. 전류밀도에 따른 전류 효율을 알아보기 위하여 전류밀도에 따른 실험적 증착 속도와 이론적 속도를 비교 분석 하였다. 도금 두께는 FE-SEM(Field Emission Scanning Electron Microscope)을 이용하여 측정 하였으며 최종적으로 $20{\mu}m{\times}20{\mu}m{\times}10{\mu}m$ 크기에 $50{\mu}m$ 피치를 가지는 straight wall 형 Sn-0.7wt%Cu 솔더 범프를 형성하고자 하였다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2014.11a
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• pp.136-137
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• 2014

주석계 전기도금액에 포함된 불소계 계면활성제는 분산 유화 소포 효과를 발휘할 수 있으며, 도금 금속 결정을 미세하게 하여 범프의 그레인 크기와 모양 특성을 개선하며, 범프의 높이 차 (WID, WIW) 감소 및 범프 내 빈 공간과 금속간 층의 균열 생성 방지에 영향을 주었음을 알 수 있었다.

• Proceedings of the Korean Reliability Society Conference
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• 2000.04a
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• pp.97-103
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• 2000

전자 산업의 발달에 따라 전자 패키지에서 소자의 소형화 및 고집적화가 가속화되고 그로 인해 interconnection 부분의 신뢰성 평가의 중요성이 나날이 증가되고 있다. 특히 이러한 interconnection 부분 중 솔더 접합부는 사용중 솔더와 UBM(Under Bump Metallurgy) 층 사이에 금속간화합물이 생성되어 접합 강도가 저하되는 것이 큰 문제로 지적되고 있다. 본 연구에서는 공정 Sn-Ag 솔더 접합부에 대해 열시효 시간에 따라 접합 강도를 측정하고 파괴 기구 및 파괴 경로의 분석을 통해 접합 강도 변화와의 연관성을 도출하고자 하였다. 그 결과 열시효 초기에는 미세 조직의 조대화 및 불균일 조대 성장이 가속화되면서 응력 및 변형 집중으로 인해 솔더 내부에서 연성 파괴가 일어나 급격한 접합 강도의 저하가 발생하였으나 금속간 화합물이 생성, 성장함에 따라 금속간 화합물 내부에서의 취성 파괴가 나타나면서 접합 강도 저하가 포화되는 경향을 보였다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.05a
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• pp.31-31
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• 2015

본 연구는, TAB(Tape Automated Bonding)접속이나 Flip Chip 접속에 의한 패캐징을 실현시키기 위해, 실리콘 웨이퍼 표면에 구리 필러 및 주석 합금을 전기 도금법으로 형성하는 전기 접점용 범프에 관한 것이다. 본 연구에서는, 균일 범프 두께, 범프 표면의 균일화, 범프 내의 보이드 발생 문제 해결, 균일한 합금 조성 및 도금 속도의 고속화를 위해, Cu 도금액 및 Sn-Ag 도금액의 첨가제에 의한 표면 형상의 제어를 중심으로 그 성능에 대해 보고한다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.04a
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• pp.109-110
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• 2007

본 연구에서는 범프를 형성하는 여러 가지 방법중 전해도금을 이용하여 Sn-Cu 솔더 범프를 형성하고자 하였다. 기초적인 도금 특성을 알아보기 위하여 전류밀도에 따른 중착속도, 도금 시간에 따른 도금두께 등을 측정하였으며, 최종적으로는 $20{\times}20{\times}10{\mu}m$ 크기에 $50{\mu}m$피치를 갖는 Sn-Cu 솔더 범프를 형성하고자 하였다.

• Progress in Superconductivity
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• v.3 no.1
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• pp.17-22
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• 2001

Practical implementation of the SFQ technology in most application requires more than single-chip-level circuit complexity. Multiple chips have to be integrated with a technology that is reliable at cryogenic temperatures and supports an inter-chip data transmission speed of tens of GHz. In this work, we have studied two basic issues in building large RSFQ circuits. The first is the reliable inter-chip SFQ pulse transfer technique using Multi-Chip-Module (MCM) technology. By noting that the energy contained in an SFQ pulse is less than an attojoule, it is not very surprising that the direct transmission of a single SFQ pulse through MCM solder bump connectors can be difficult and an innovative technique is needed. The second is the recycling of the bias currents. Since RSFQ circuits are dc current biased the large RSFQ circuits need serial biasing to reduce the total amount of current input to the circuit.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.59-64
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• 2013

In-situ annealing tests of Cu/Ni/Au/Sn-Ag/Cu micro-bump for 3D IC package were performed in an scanning electron microscope chamber at $135-170^{\circ}C$ in order to investigate the growth kinetics of intermetallic compound (IMC). The IMC growth behaviors of both $Cu_3Sn$ and $(Cu,Ni,Au)_6Sn_5$ follow linear relationship with the square root of the annealing time, which could be understood by the dominant diffusion mechanism. Two IMC phases with slightly different compositions, that is, $(Cu,Au^a)_6Sn_5$ and $(Cu,Au^b)_6Sn_5$ formed at Cu/solder interface after bonding and grew with increased annealing time. By the way, $Cu_3Sn$ and $(Cu,Au^b)_6Sn_5$ phases formed at the interfaces between $(Cu,Ni,Au)_6Sn_5$ and Ni/Sn, respectively, and both grew with increased annealing time. The activation energies for $Cu_3Sn$ and $(Cu,Ni,Au)_6Sn_5$ IMC growths during annealing were 0.69 and 0.84 eV, respectively, where Ni layer seems to serve as diffusion barrier for extensive Cu-Sn IMC formation which is expected to contribute to the improvement of electrical reliability of micro-bump.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.9-15
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• 2009

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.