• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.23-29
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• 2006

Ultrasonic soldering of Si-wafer to FR-4 PCB at ambient temperature was investigated. The UBM of Si-substrate was Cu/ Ni/ Al from top to bottom with thickness of $0.4{\mu}m,\;0.4{\mu}m$, and $0.3{\mu}m$ respectively. The pad on FR-4 PCB comprised of Au/ Ni/ Cu from top to bottom with thickness of $0.05{\mu}m,\;5{\mu}m$, and $18{\mu}m$ respectively. Sn-3.5wt%Ag foil rolled to $100{\mu}m$ was used for solder. The ultrasonic soldering time was varied from 0.5 s to 3.0 s and the ultrasonic power was 1,400 W. The experimental results show that a reliable bond by ultrasonic soldering at ambient temperature was obtained. The shear strength increased with soldering time up to a maximum of 65 N at 2.5 s. The strength decreased to 34 N at 3.0 s because cracks were generated along the intermetallic compound between Si-wafer and Sn-3.5wt%Ag solder. The Intermetallic compound produced by ultrasonic soldering between the Si-wafer and the solder was $(Cu,Ni)_{6}Sn_{5}$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.7-15
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• 2006

In-situ observation of electromigration in thin film pattern of 63Sn-37Pb solder was performed using a scanning electron microscope system. The 63Sn-37Pb solder had the incubation stage of electromigration for edge movement when the current density of $6.0{\times}10^{4}A/cm^2$ was applied the temperature between $90^{\circ}C\;and\;110^{\circ}C$. The major diffusion elements due to electromigration were Pb and Sn at temperatures of $90-110^{\circ}C\;and\;25-50^{\circ}C$, respectively, while no major diffusion of any element due to electromigration was detected when the test temperature was $70^{\circ}C$. The reason was that both the elements of Sn and Pb were migrated simultaneously under such a stress condition. The existence of the incubation stage was observed due to Pb migration before Sn migration at $90-110^{\circ}C$. Electromigration behavior of 63Sn-37Pb solder had an incubation time in common for edge drift and void nucleation, which seemed to be related the lifetime of flip chip solder bump. Diffusivity with $Z^*$(effective charges number) of Pb and Sn were strongly affect the electromigration-induced major diffusion element in SnPb solder by temperature, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.1-10
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• 2001

Chip-on-glass(COG) mounting of area array electronic packages was attempted by heating the rear surface of a contact pad film deposited on a glass substrate. The pads consisted of an adhesion (i.e. Cr or Ti) and a top coating layer(i.e. Ni or Cu) were healed by the UV laser beam transmitted through the glass substrate. The lather energy absorbed on the pad raised the temperature of a solder ball which is in physical contact with the pad, and formed a reflowed solder bump. The effects of the adhesion and top coating layer on the laser reflow soldering were studied by measuring temperature profile of the ball during the laser heating process. The results were discussed based on the measurement of reflectivity of the adhesion layer. In addition, the microstructures of solder bumps and their mechanical properties were examined.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.1-7
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• 2008

We studied a growth behavior of Intermetallic compounds(IMCs) during solder bumping with two reflow methods. Ti(50 nm), Cu($1{\mu}m$), Au(50 nm) and Ti(50 nm) thin films were deposited on $SiO_2$/Si wafer using the DC magnetron sputtering system as the under bump metallization(UBM). And the $5{\mu}m$ thick Cu bumps and $20{\mu}m$ thick Sn bumps were fabricated on UBM by electroplating. Sn bumps were reflowed in RTA(Rapid Thermal Annealing) system and convection reflow oven. When RTA system was used, reflow was possible without using flux and IMC thickness formed in the solder interface was thinner than that of a convectional method.

• Journal of Surface Science and Engineering
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• v.36 no.5
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• pp.373-378
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• 2003

With increasing environmental concerns, application of lead-free solder and fluxless soldering process have been taken attention from the electronic packaging industry. Plasma treatment is one of the soldering methods for the fluxless soldering, and it can prevent environmental pollution cased by flux. On this study fluxless soldering process under $Ar-H_2$plasma using lead free solders such as Sn-3.5 wt%Ag, Sn-3.5 wt%Ag-0.7 wt%Cu and Sn-37%Pb for a reference was investigated. As the plasma reflow has higher soldering temperature than normal air reflow, the effects of UBM(Under Bump Metallization) thickness on the interfacial reaction and bonding strength can be critical. Experimental results showed in case of the thin UBM, Au(20 nm)/Cu(0.3 $\mu\textrm{m}$)/Ni(0.4 $\mu\textrm{m}$)/Al(0.4 $\mu\textrm{m}$), shear strength of the soldered joint was relatively low as 19-27㎫, and it's caused by the crack observed along the bonded interface. The crack was believed to be produced by the exhaustion of the thin UBM-layer due to the excessive reaction with solder under plasma. However, in case of thick UBM, Au(20 nm)/Cu(4 $\mu\textrm{m}$)/Ni(4 $\mu\textrm{m}$)/Al(0.4 $\mu\textrm{m}$), the bonded interface was sound without any crack and shear strength gives 32∼42㎫. Thus, by increasing UBM thickness in this study the shear strength can be improved to 50∼70%. Fluxed reflow soldering under hot air was also carried out for a reference, and the shear strength was 48∼52㎫. Consequently the fluxless soldering with plasma showed around 65∼80% as those of fluxed air reflow, and the possibility of the $Ar-H_2$ plasma reflow was evaluated.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.35-39
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• 2012

We studied interfacial reaction and bonding characteristics of a flip chip bonding with the viewpoint of formation behavior of intermetallic compounds. For this purpose, Sn-0.7Cu and Sn-3Cu solders were reflowed on the Al/Cu and Al/Ni UBMs. When Sn-0.7Cu was reflowed on the Al/Cu UBM, no intermetallic compounds were formed at the solder/UBM interface. The $Cu_6Sn_5$ intermetallic compounds formed by reflowing Sn-3Cu solder on the Al/Cu UBM were spalled from the interface, resulting in delamination of the solder/UBM interface. On the other hand, the $(Cu,Ni)_6Sn_5$ intermetallic compounds were formed by reflowing of Sn-0.7Cu and Sn-3Cu on the Al/Ni UBM and the interfacial bonding between the Sn-Cu solders and the Al/Ni UBM was kept stable.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.11-17
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• 2009

The drop impact reliability comes to be important for evaluation of the life time of mobile electronic products such as cellular phone. The drop impact reliability of solder joint is generally affected by the kinds of pad and reflow number, therefore, the reliability evaluation is needed. Drop impact test proposed by JEDEC has been used as a standard method, however, which requires high cost and long time. The drop impact reliability can be indirectly evaluated by using high speed shear test of solder joints. Solder joints formed on 3 kinds of surface finishes OSP (Organic Solderability Preservation), ENIG (Electroless Nickel Immersion Gold) and ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) was investigated. The shear strength was analysed with the morphology change of intermetallic compound (IMC) layer according to reflow number. The layer thickness of IMC was increased with the increase of reflow number, which resulted in the decrease of the high speed shear strength and impact energy. The order of the high speed shear strength and impact energy was ENEPIG > ENIG > OSP after the 1st reflow, and ENEPIG > OSP > ENIG after 8th reflow.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.53-57
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• 2011

In the modern packaging technologies highly condensed metal interconnects are typically formed by highcost processes. These methods inevitably require the precise controls of mutually dependant process parameters, which usually cause the difficulty of the change in the layout design for interconnects of chip to-chip, or chip-to-substrate. In order to overcome these problems, the unique concept and methodology of self-assembly even in micro-meter scale were developed. In this report we focus on the factors which influenced the self-formed bumps by analyzing the phenomenon experimentally. In case of RMA flux, homogenous pattern was obtained in both plain surface and cross-section surface observation. By using RA flux, the phenomena were accelerated although the self-formtion results was inhomogenous. With ussage of moderate RA flux, reaction rate of the self-formation was accelerated with homogeneous pattern.

• Journal of the Korean Society of Industry Convergence
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• v.3 no.1
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• pp.69-75
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• 2000

Multichip packages are comprised of dissimilar materials which expand at different rates on heating. The differential expansion must be accommodated by the various structural elements of the package. A types of heat exposures occur operation cycles. This study presents a finite element analysis simulation of flip-chip among multichip. The effects of geometries and material properties on the reliability were estimated during the analysis of temperature and thermal stress of flip-chip. From the results, it could be obtained that the more significant parameters to the reliability of flip-chip arc chip power cycle, heat convection and height of solder bump.