• Proceedings of the Korea Multimedia Society Conference
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• 2003.11b
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• pp.557-560
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• 2003

In this paper, we developed an editor and running engine for the SoftPLC. LD is the most popular standard IEC 1131-3 PLC language in Korea and used over 90% among the 5 PLC languages. In this paper, we have developed the ISPLC(Intelligent Agent System based Software Programmable Logic Controller). In ISPLC system, LD programmed by a user is converted to IL, which is one of intermediate codes, and IL is converted to the standard C code which can be used in a commercial editor such as visual C++. In ISPLC, the detection of logical error in high level programming(C) is more efficient than PLC programming itself. ISPLC provide easy programming platform to such beginner as well as professionals. The study of code conversion of LD-> U->C is firstly tried in the world as well as KOREA.

• Journal of Integrative Natural Science
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• v.12 no.4
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• pp.105-115
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• 2019

In this paper, a prediction system is proposed to control the brightness of smart street lamps by predicting the moving path through the reduction of consumption power and information of pedestrian's past moving direction while meeting the function of existing smart street lamps. The brightness of smart street lamps is adjusted by utilizing the walk tracking vector and soft hand-off characteristics obtained through the motion sensing sensor of smart street lamps. In addition, the motion vector is used to analyze and predict the pedestrian path, and the GPU is used for high-speed computation. Pedestrians were detected using adaptive Gaussian mixing, weighted difference imaging, and motion vectors, and motions of pedestrians were analyzed using the extracted motion vectors. The preprocessing process using linear interpolation is performed to improve the performance of the proposed prediction system. Fuzzy prediction system and neural network prediction system are designed in parallel to improve efficiency and rough set is used for error correction.

• Proceedings of the KWS Conference
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• 2000.04a
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• pp.99-102
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• 2000

Conventionally, ZVS FB DC/DC converter was controlled by monolithic IC UC3879, which includes the functions of oscillator, error amplifier and phase-shift circuit. Also, microprocessor and DSP have been widely used for the remote control and for the immediate waveform control in ZVS FB DC/DC converter. However the conventional microprocessor controller is complex and difficult to control because the controller consists of analog and digital parts. In the case of the control of FB DC/DC converter, the output is required of driving a direct signal to the switch drive circuits by the digital controller. So, this paper presents the method and realization of designing the digital-to-phase shift PWM circuit controlled by DSP (TMX320C32) in a 2,500A, 40㎾ WS FB DC/DC converter.

• International journal of advanced smart convergence
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• v.9 no.3
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• pp.141-144
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• 2020

Iterative decision feedback equalizer (IDFE) is a recursive equalization technique that can help to achieve an additional performance gain for the system by combining iterative channel decoding and interference cancellation. In a single carrier-based system, the intersymbol interference (ISI) is a critical problem that must be resolved since it causes frequency selective fading. Based on the idea of sharing the estimated information in the process of iteration, IDFE is considered as an efficient solution to improve the robustness of the system performance on the ISI channel. In this paper, the IDFE is applied on single carrier FDMA (SC-FDMA) system to evaluate the performance under ISI channel. The simulation results illustrate that IDFE helps to improve the performance of the SC-FDMA system, especially with long delay spread channels.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.156-160
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• 2014

Thresholding in frequency domain is a simple and effective noise reduction technique. Determination of the threshold is critical to the image quality. The optimal threshold minimizing the Mean Square Error (MSE) is chosen adaptively in the wavelet domain; we utilize an equation of the MSE for the soft-thresholded signal and the histogram of wavelet coefficients of the original image and noisy image. The histogram of the original signal is estimated through the deconvolution assuming that the probability density functions (pdfs) of the original signal and the noise are statistically independent. The proposed method is quite general in that it does not assume any prior for the source pdf.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.12
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• pp.100-108
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• 2002

This paper describes the development of adult authentication system using numerical recognition. Nowadays, the automats are very popular and they are dealing in many item suck as coffee, soft drinks, alcoholic drinks and cigarettes, etc. Among these items, some are harmful to the minor, and so the sale of these to the minor must be prohibited. In relation to this, adult authentication system is required to be equipped to the automat which deals in items harmful to minor. According to these demands, we develop the adult authentication system. This system capture the image of a residence certificate card by the identification card-reader, and recognize its numbers and identify it as adult or minor by main computer, where numeral recognition is accomplished by using image processing methods and neural network recognizer. The characteristic test of the system is carried out, and its result reveals that the system has the error of less than 1%. Thus, It is thought that the system can be used for identifying adult in the automats.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.190-196
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• 2009

In this paper, performance of a turbo-coded OFDM system is analyzed and simulated in a power line communication channel. Since the power line communication system typically operates in a hostile environment, turbo code has been employed to enhance reliability of transmitted data. The performance is evaluated in terms of bit error probability. As turbo decoding algorithms, MAP (maximum a posteriori), Max-Log-MAP, and SOVA (soft decision Viterbi output) algorithms are chosen and their performances are compared. From simulation results, it is demonstrated that Max-Log-MAP algorithm is promising in terms of performance and complexity. It is shown that performance is substantially improved by increasing the number of iterations and interleaver length of a turbo encoder. The results in this paper can be applied to OFDM-based high-speed power line communication systems.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.567-570
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• 1989

A constant V/F control system of voltage contrlled PWM inverter has a unstable operation of the low- speed and the light-load. In this paper, the authors propose stability control with idealized operation of induction motor by the neglect of primary leakage inductance and resistance. Also ldealized operation system is adopted voltage error, feed back impedance circuit, and increasing resistance from dead time of switching is compensated by the soft ware with u-processors. The proposed simulation of the idealized control method is proved at the low-speed operation for three phase induction motor.

• The Journal of Information Technology
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• v.3 no.1
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• pp.29-36
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• 2000

Viterbi decoder is a maximum likelihood decoding method for convolution coding used in satellite and mobile communications. In this paper, a Viterbi decoder with constraint length of K=7, 3 bit soft decision and traceback depth of ${\Gamma}=96$ for convolution code is implemented using VHDL. The hardware size of designed decoder is reduced by 4 bit pre-traceback in the survivor memory.

• The Magazine of the IEIE
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• v.24 no.6
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• pp.38-49
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• 1997

0.4mm Resign Rule의 Super Low Power Dissipation, Low Voltage. Operation-5- Full CMOS SRAM Cell을 개발하였다. Retrograde Well과 PSL(Poly Spacer LOCOS) Isolation 공정을 사용하여 1.76mm의 n+/p+ Isolation을 구현하였으며 Ti/TiN Local Interconnection을 사용하여 Polycide수준의 Rs와 작은 Contact저항을 확보하였다. p-well내의 Boron이 Field oxide에 침적되어 n+/n-well Isolation이 취약해짐을 Simulation을 통해 확인할 수 있었으며, 기생 Lateral NPN Bipolar Transistor의 Latch Up 특성이 취약해 지는 n+/n-wellslze는 0.57mm이고, 기생 Vertical PNP Bipolar Transistor는 p+/p-well size 0.52mm까지 안정적인 Current Gain을 유지함을 알 수 있었다. Ti/TiN Local Interconnection의 Rs를 Polycide 수준으로 낮추는 것은 TiN deco시 Power를 증가시키고 Pressure를 감소시킴으로써 실현할 수 있었다. Static Noise Margin분석을 통해 Vcc 0.6V에서도 Cell의 동작 Margin이 있음을 확인할 수 있었으며, Load Device의 큰 전류로 Soft Error를 개선할수 있었다. 본 공정으로 제조한 1M Full CMOS SRAM에서 Low Vcc margin 1.0V, Stand-by current 1mA이하(Vcc=3.7V, 85℃기준) 를 얻을 수 있었다.