• Journal of electromagnetic engineering and science
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• 제11권4호
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• 한국전자파학회논문지
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• 제13권7호
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• pp.633-640
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• 2002

본 논문에서는 이중공진 칩 meander 안테나를 제안하였다. 제안된 안테나는 기존 meander 안테나의 소형화 특성을 유지하면서 인접한 주파수에서 이중공진하는 특징을 갖는다. LTCC-MLC 공정을 이용하여 제작하였고, 2.20 GHz와 2.883 GHz에서 이중공진(주파수비=1.35)하며, meander 패치의 크기는 15.7 mm $\times$ 6.52 mm( 0.32 λg $\times$ 0.133 λg)이다. 그리고 이중공진 meander 안테나의 추가적인 소형화를 위해 3차원 구조를 제안한다. 이 3차원 구조를 이용하여 약 50 %의 크기를 추가적으로 소형화하였다. 전류분포를 통해 제안된 안테나가 이중공진하는 원리를 확인하였고, 제작된 안테나의 반사손실 및 방사패턴의 특성을 분석하였다.

• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.840-846
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• 2000

In this work, small-size, high-performance solenoid-type RF chip inductors utilizing a low-loss Al$_2$O$_3$core material were investigated. The size of the chip inductors fabricated in this work were 15$\times$10$\times$0.7㎣, 2.1$\times$1.5$\times$10㎣, and 2.4$\times$2.0$\times$1.4㎣ and copper (Cu) wire with 40 ㎛ diameter was used as the coils. High frequency characteristics of the inductance, quality factor, and impedance of developed inductors were measured suing an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). It was observed that the developed inductors with the number of turns of 7 have the inductance of 33 to 100nH and exhibit the self-resonant frequency (SRF) of .26 to 1.1 GHz. The SRF of inductors decreases with increasing the inductance and the inductors have the quality factor of 60 to 80 in the frequency range of 300 MHz to 1.1 GHz. In this study, small-size solenoid-type RF chip inductors with high inductance and high quality factor were fabricated successfully. It is suggested that the thin film-type inductor is necessary to fabricate the smaller size inductors at the expence of inductance and quality factor values.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.131-135
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• 2002

본 연구에서는 개인 통신기의 핵심부품인 초소형 세라믹 칩 안테나 (SMD형) 개발의 무선회로 설계 기술, 초소형 설계기술, 표면실장기술, 소형화 SMD기술, Test기술 및 설계기반 마련 및 대외 경쟁력 있는 초소형 세라믹 칩 안테나 (SMD형) 개발의 초소형화 기술을 확보하였다. 중심주파수는 2442.5MHz(Type), 반사손실은 -l0dB이하, 정재파비는 2max, xy의 최대 이득은 -2dB 이상, size는 0.05ccmax이다.

• 한국전기전자재료학회논문지
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• 제17권3호
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• pp.340-347
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• 2004

Ultra-small size, high-performance, solenoid-type RF chip inductors utilizing low-loss A1$_2$O$_3$ core materials were investigated. The dimensions of the RF chip inductors fabricated were 1.0mm${\times}$0.5mm${\times}$0.5mm and copper coils were used. The materials (96％ A1$_2$O$_3$) and shape (I-type) of the core, the diameters (40${\mu}{\textrm}{m}$) and position (middle) of the coil, and the lengths (0.35mm) of solenoid were determined by a high-frequency structure simulator (HFSS) to maximize the performance of the inductors. The high-frequency characteristics of the inductance (L) and quality-factor (Q) of the developed inductors were measured using a RF impedance/material analyzer (E4991A with E16197A test fixture). The developed inductors exhibit an inductance of 11 to 11.3nH and a qualify factor of 22.3 to 65.7 over the frequency ranges of 250 MHz to 1.7 GHz, and show results comparable to those measured for the inductors prepared by Coilcraft$^{TM}$. The simulated data described the high-frequency data of the L and Q of the fabricated inductors well.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• ETRI Journal
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• 제27권2호
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• pp.133-139
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• 2005

A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 ${\mu}$ gate-length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4-inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2mm${\times}$ 2mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1mm${\times}$ 2mm. The frequency doubler achieved an output power of -6 dBm at 76.5 GHz with a conversion gain of -16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2mm ${\times}$ 1.2mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W-band.

• Journal of the Korean Wood Science and Technology
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• 제43권2호
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• pp.186-195
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• 2015

This study aims at modeling the rotary drying of wood chips in co-current mode and estimating the drying time of larch (Larix kaemferi) wood chip. Drying data were obtained in a lab. scale fixed bed dryer operating with an air velocity of 1 m/sec. and at hot air inlet temperatures of $100^{\circ}C$, $200^{\circ}C$, and $300^{\circ}C$. The lab. scale fixed-bed drying rates for small, medium and large size larch wood chips that had been dried from 40% wet-based moisture content (MC) to 10% MC at $200^{\circ}C$ drying temperature were 17.3 %/min., 10.2 %/min. and 5.5 %/min., respectively. It was predicted that larch large size wood chips could be dried from 40% MC to 10% MC in about 23.0, 34.6, and 44.7 minutes at $300^{\circ}C$, $200^{\circ}C$ and $150^{\circ}C$, respectively. Expected drying times for medium size chips were about 8.6, 11.2 and 13.2 minutes and those for small size chips were 4.3, 5.5 and 6.4 minutes, respectively.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.39-45
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• 2000

A small camera module fabricated by including bare chip bonding methods is utilized to realize advanced mobile devices. One of the driving forces is the TOG (Tape On Glass) bonding method which reduces the packaging size of the image sensor clip. The TOG module is a new thinner and smaller image sensor module, using flip chip interconnection method with the ACP (Anisotropic Conductive Paste). The TOG production process was established by determining the optimum bonding conditions for both optical glass bonding and image sensor clip bonding lo the flexible PCB. The bonding conditions, including sufficient bonding margins, were studied. Another bonding method is the flip chip bonding method for DSP (Digital Signal Processor) chip. A new AC\ulcorner was developed to enable the short resin curing time of 10 sec. The bonding mechanism of the resin curing method was evaluated using FEM analysis. By using these flip chip bonding techniques, small camera module was realized.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
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• pp.681-684
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• 2008

본 논문에서는 이동통신용 단말기 PCB Layout 위에 내장형 Chip 안테나를 직접 설계하여 DCS($1.71{\sim}1.88GHz$) 대역, PCS($1.75{\sim}1.87GHz$) 대역 및 UPCS($1.85{\sim}l.99GHz$) 대역에서 공통으로 사용할 수 있는 이동통신용 트리플밴드 Chip 안테나를 설계하였다. 설계 제작된 안테나는 PCB 기판위에 탑재되는 안테나로서 안테나의 양측면에 씌워진 상부 방사패치와 하부 방사패치로 구성되어 있으며, 상하부 방사패치의 용량과 길이를 조절함으로서 DCS, PCS, UPCS대역에서 공동으로 사용할 수 있는 트리플 안테나를 제안했다. 안테나의 크기는 $19mm{\times}4mm{\times}1.6mm$으로 설계하여 매우 소형화시켰으며, Chip 안테나의 단점인 좁은 대역폭을 크게 개선시켰다. 설계한 안테나의 대역폭은 정재파비2 이하를 기준으로 DCS, PCS, UPCS 대역을 모두 충족하였으며, 전체 대역폭은 $1.71GHz{\sim}1.99GHz$의 15.1%의 주파수 대역폭을 얻었다.