• Journal of Electrical Engineering and Technology
• /
• v.11 no.1
• /
• pp.157-166
• /
• 2016

In this paper, a new sag and peak voltage detector is proposed for a single-phase inverter using delta square operation. The conventional sag detector is from a single-phase digital phase-locked loop (DPLL) that is based on d-q transformations using an all-pass filter (APF). The d-q transformation is typically used in the three-phase coordinate system. The APF generates a virtual q-axis voltage component with a 90° phase delay, but this virtual phase cannot reflect a sudden change in the grid voltage at the instant the voltage sag occurs. As a result, the peak value is drastically distorted, and it settles down slowly. A modified APF generates the virtual q-axis voltage component from the difference between the current and the previous values of the d-axis voltage component in the stationary reference frame. However, the modified APF cannot detect the voltage sag and peak value when the sag occurs around the zero crossing points such as 0° and 180°, because the difference voltage is not sufficient to detect the voltage sag. The proposed algorithm detects the sag voltage through all regions including the zero crossing voltage. Moreover, the exact voltage drop can be acquired by calculating the q-axis component that is proportional to the d-axis component. To verify the feasibility of the proposed system, the conventional and proposed methods are compared using simulations and experimental results.

• The Journal of the Korea Contents Association
• /
• v.6 no.4
• /
• pp.1-10
• /
• 2006

In this paper, a broadband RF module is designed and tested for 2.4GHz band applications. The RF module is composed of a low noise amplifier (LNA) with a three stage amplifier, a single ended gate mixer, matching circuits, a hairpin line band pass filter and a Chebyshev low pass filter to convert the radio frequency (RF) into the intermediate frequency (IF). The LNA has a high gain and stability, and the single ended gate mixer has a high conversion gain and wide dynamic range. In the analysis of the broadband RF module, the composite harmonic balance technique is used to analyze the operating characteristics of an RF module circuit. The RF module has a 55.2dB conversion gain with a 1.54dB low noise figure, $-120{\sim}-60dBm$ wide RF power dynamic range, -60dBm low harmonic spectrum and a good isolation factor among the RF, IF, and local oscillator (LO) ports.

• Journal of the Korea Computer Industry Society
• /
• v.6 no.5
• /
• pp.757-766
• /
• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.38 no.4
• /
• pp.20-30
• /
• 2001

A novel 200 MHz CMOS transconductor using translinear cells is proposed. The proposed transconductor consists of voltage followers and current followers based on translinear cells and a resistor. For wide applications, a single-input single-output, a single-Input differential-output, and a fully-differential transconductor are systematically designed, respectively. The theory of operation is described and computer simulation results are used to verify theoretical predictions. The results show that the fully-differential transconductor has a linear input voltage range of ${\pm}2.7$ V, a 3 dB frequency of 200 MHz, and a temperature coefficient of less than 41 $ppm/^{\circ}C$ at supply voltages of ${\pm}3$ V. In order to certify the applicability of the fully-differential transconductor, A ladder-type 3th-order cllitic low pass filter is also designed based on the inductance simulation method. The filter has a ripple bandwidth of 22 MHz, a pass-band ripple of 0.36 dB, and a cutoff frequency of 26 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.5
• /
• pp.538-544
• /
• 2011

This paper presents a compact single balanced diode mixer fabricated using a 0.1 ${\mu}M$ GaAs p-HEMT commercial process for an E-band frequency up/down converter. This mixer includes a LO balun employing a Marchand balun with a good RF performance. In order to improve the port-to-port isolation, a high pass filter and a low pass filter are include in this mixer at the RF and IF ports, respectively. The fabricated mixer with a very compact size of 0.58 mm2(0.85 mm${\times}$0.68 mm) exhibits a conversion loss of 8～12 dB and an input P1dB of 1～5 dBm at the LO power of 10 dBm from 71～86 GHz.

• Journal of IKEEE
• /
• v.26 no.2
• /
• pp.271-279
• /
• 2022

This paper proposes an advanced dead-time compensation method for dual inverter with a floating capacitor. The dual inverter with floating capacitor is composed of double two-level inverters and a bulk electrolytic capacitor. The output voltage of the dual inverter is dropped by the conduction voltage of the power semiconductors. The voltage drop and dead-time cause the fundamental and harmonic distortions of output currents. When supplied power for OEW-load is low, the dual inverter operates as single inverter for effective operation. The dead-time compensation method for the dual inverter operated as single inverter is needed for reliability. The proposed method using band pass filter in this paper compensates dead-time, dead-time error and changed voltage drop error of power semiconductors for the dual inverter and dual inverter operated as single inverter. The effectiveness of the proposed method is verified by simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.12B
• /
• pp.2407-2414
• /
• 1999

This paper introduces the concept of warped discrete cosine transform (WDCT) and an image compression algorithm based on the WDCT. The proposed WDCT is a cascade connection of a conventional DCT and all-pass filters whose parameters can be adjusted to provide frequency warping. In the proposed image compression scheme, the frequency response of the all-pass filter is controlled by a set of parameters with each parameter for a specified frequency range. For each image block, the best parameter is chosen from the set and is sent to the decoder as a side information along with the result of corresponding WDCT computation. For actual implementation, the combination of the all-pass IIR filters and the DCT can be viewed as a cascade of a warping matrix and the DCT matrix, or as a filter bank which is obtained by warping the frequency response of the DCT filter bank. Hence, the WDCT can be implemented by a single matrix computation like the DCT. The WDCT based compression, outperforms the DCT based compression, for high bit rate applications and for images with high frequency components.

• Journal of the Korean Ceramic Society
• /
• v.39 no.2
• /
• pp.210-215
• /
• 2002

Optical Band-pass Filter(BPF) for the selected wavelength of 4300 nm was designed and fabricated on Si wager by alternately depositing Ge and $SiO_2$ thin layers by an electron beam evaporation technique. The fabricated BPF showed the optical transmittance characteristics of 58.2% with FWHM(Full Width at Half Maximum) of 204 nm at 4300 nm, but showed the transmittance less than 5% due to the reflectance over all the wavelength ranges except 4300 nm band. The $CO_2$ sensitivity of BPF was investigated with the transmittance as a function of $CO_2$ gas concentration using a sensing cell attached to FT-IR instrument. The transmittance of BPF was almost linearly decreased with increasing of $CO_2$ concentration in the range of from 500 to 5000 ppm. The sensing structure using double BPFs showed higher slop of transmittance vs $CO_2$ concentration, and thus higher gas sensitivity than that using a single BPF, even though the former had relatively lower transmittance.

• Journal of Welding and Joining
• /
• v.31 no.1
• /
• pp.65-70
• /
• 2013

Finite element analysis and welding experiments were performed to evaluate deformation aspect for Flux Cored Arc Welding(FCAW) and Electro Gas Welding(EGW). Numerical researches of FCAW and EGW were performed considering the difference of number of welding pass and welding direction to arc flow. To perform the numerical study of FCAW and EGW, number of welding pass and welding direction to arc flow were considered in the finite element model. FCAW process requires multi pass and its welding direction is vertical to welding torch. On the other hand, EGW process requires single pass and its welding direction is parallel to welding torch. The difference of welding direction and heat input was considered in the finite element analysis. In FCAW process, Goldak's double ellipsoidal heat input model was adopted. In the EGW process, Hemi-spherical power density distribution was adopted. In the results of experiment and finite element analysis, angular deformation of FCAW process is larger than that of EGW process.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.45 no.6
• /
• pp.1-8
• /
• 2008

This paper introduces three efficient frame selection schemes to reduce the computation complexity for the multi-reference and variable block size Motion Estimation (ME). The proposed RSP (Reference Selection Pass) scheme can minimize the overhead of frame selection. The MFS (Modified Frame Selection) scheme can reduce the number of search points about 18% compared with existing schemes considering the motion of image during the reference frame selection process. In addition, the TPRFS (Two Pass Reference frame Selection) scheme can minimize the frame selection operation for the variable block size ME in H.264/AVC using the character of selected reference frame according to the block size. The simulation results show the proposed schemes can save up to 50% of the ME computation without degradation of image Qualify. Because the proposed schemes can be separated from the block matching process, they can be used with any existing single reference fast search algorithms.