• International Journal of Railway
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• v.2 no.2
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• pp.70-79
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• 2009

An optimal driving strategy of a train in a long journey on a nonsteep track has four phases: an initial power phase, a long hold speed phase, a coast phase and a final brake phase. The majority of the journey is speed holding. On a track with steep gradients, it becomes necessary to vary the strategy around steep sections of track because it is not possible to hold a constant steep on steep track. Instead we must interrupt the speed hold phase with a power phase. The aim of this paper is to show that there is a unique power phase that satisfies the necessary conditions for an optimal journey. The problem is developed and solved for various cases, from a simple single steep gradient to a complicated multiple steep gradient section. For each case, we construct a set of new conditions for optimality of the power phase that minimises the energy used during the power phase subject to a weighted time penalty. We then use the new necessary conditions to develop a calculate scheme for finding an optimal power phase for a steep incline. We also present an example to confirm the uniqueness of an optimal power phase.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.67-74
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• 2004

In this paper, a 3.3V 8-bit 500MSPS based on an interpolation architecture CMOS A/D converter is designed. In order to overcome the problems of high speed operation, a novel pre-amplifier, a circuit for the Reference Fluctuation, and an Averaging Resistor are proposed. The proposed Interpolation A/D Converter consists of Track ＆ Hold, four resistive ladders with 256 taps, 128 comparators, and digital blocks. The proposed A/D Converter is based on 0.35um 2-poly 4-metal N-well CMOS technology. The A/D Converter dissipates 440 mW at a 3.3 Volt single power supply and occupies a chip area of 2250um x 3080um.