• 대한기계학회논문집A
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• 제26권8호
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• pp.1545-1551
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• 2002

The optical storage device has recently experienced significant improvement, especially for the aspects of high capacity and fast transfer rate. However, it is necessary to study a new shape of air bearing surface for the rotary type actuator because the optical storage device has the lower access time than that of HDD (Hard Disk Drives). In this study, we proposed the air bearing shape by using SA (Simulated Annealing) algorithm which is very effective to achieve the global optimum instead of many local optimums. The objective of optimization is to minimize the deviation in flying height from a target value 100nm. In addition, the pitch and roll angle should be maintained within the operation limits.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.731-734
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.805-808
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.545-548
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• 1998

Thin film SOI(Silicon-On-Insulator) devices exhibit floating body effect. In this paper, SOI NMOSFET is proposed to solve this problem. Some part of gate oxide was considered to be 30nm~80nm thicker than the other normal gate oxide and simulated with TSUPREM-4. The I-V characteristics were simulated with 2D MEDICI mesh. Since part of gate oxide has different oxide thickness in proposed device, the gate electric field strength is not the same throught the gate and consequently the reduction of current kink effect is occurred.

• 전자공학회논문지A
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• 제29A권8호
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• pp.71-77
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• 1992

According to increasing the doping concentration in p-n junction, a tunneling current through trap as well as SRH(Shockley-Read-Hall) generation-recombination current in depletion region occurs. It is the tunneling current that is a dominant current at the forward bias. In this paper, the new tunneling-recombination equation is derived. The thermal generation-recombination current and tunneling current though trap can be easily calculated at the same time because this equation has the same form as the SRH generation-recombination equation. For the validity of this equation, 2 kind of samples are simulated. The one is $n^{+}$-p junction device fabricated with MCT(Mercury Cadmium Telluride, mole fraction=0.29), the other Si n$^{+}-p^{+}$ junction. From the results for MCT $n^{+}$-p junction device and comparing the simulated and expermental I-V characteristics for Si n$^{+}-p^{+}$ junction, it is shown that this equation is a good description for tunneling through trap and thermal generation-recombination current calculation.

• 전기전자학회논문지
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• 제10권2호통권19호
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• pp.141-148
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• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• 전자공학회논문지A
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• 제30A권4호
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• pp.40-50
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• 1993

In this paper, MODFET devices with various gate length are simulated using the Monte-Carlo method. The number of superparticle is 5000 and the Poisson equation is solved to obtain field distribution. The structure of MODFET is n-AlGaAs/i-AlGaAs/iGaAs and doping concentration of n-AlGaAs layer is 1${\times}10^{17}/cm^{3}$ and the thickness is 500.angs., and the thickness of i-AlGaAs is 50$\AA$. The devices with gate length 0.2$\mu$m, 0.5$\mu$m, 1.0$\mu$m respctively are simulated and the current-voltage curves and transport characteristics of that devices are obtained. Occupancy of each subband and electron energy distribution and conduction energy band in channel have been analyzed to obtain transport characteristics, and particles transposed from source to drain have been analyzed to current-voltage curves. Current level is highest for the device of Lg=0.2$\mu$m and transconductance of this device is 310mS/mm.

• 센서학회지
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• 제22권5호
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• pp.364-368
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• 2013

Vibrational energy harvester based on piezoelectricity has been expected to be the dominant energy harvesting technology due to the advantages of high conversion efficiency, light weight and small size, night operation, etc. Its commercialization is just around the corner but the integration with power management electronics should be solved in advance. In this paper, therefore, fully-integrated design environment for piezoelectric energy harvesting systems is presented to assist co-design with the power management electronics. The proposed design environment is capable of analyzing the energy harvester including the package-induced damping effects and simulating the device and its power management electronics simultaneously. When the developed design environment was applied to the fabricated device, the simulated resonant frequency matched well with the experimental result with a difference of 2.97% only. Also, the complex transient response was completed in short simulation time of 3,001 seconds including the displacement distribution over the device geometry. Furthermore, a full-bridge power management circuit was modeled and simulated with the energy harvester simultaneously. Therefore the proposed, fully-integrated design environment is accurate and fast enough for the contribution on successful commercialization of piezoelectric energy harvester.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 2001년도 춘계학술발표회요약집
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• pp.365-365
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• 2001

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.537-538
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• 2007